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hw/loongarch: Add LoongArch ipi interrupt support(IPI)

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This patch realize the IPI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-32-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang 2022-06-06 20:43:21 +08:00 • committed by Richard Henderson
parent a8a506c390
commit f6783e3438
8 changed files with 307 additions and 0 deletions
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52
include/hw/intc/loongarch_ipi.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* LoongArch ipi interrupt header files
*
* Copyright (C) 2021 Loongson Technology Corporation Limited
*/
#ifndef HW_LOONGARCH_IPI_H
#define HW_LOONGARCH_IPI_H
#include "hw/sysbus.h"
/* Mainy used by iocsr read and write */
#define SMP_IPI_MAILBOX 0x1000ULL
#define CORE_STATUS_OFF 0x0
#define CORE_EN_OFF 0x4
#define CORE_SET_OFF 0x8
#define CORE_CLEAR_OFF 0xc
#define CORE_BUF_20 0x20
#define CORE_BUF_28 0x28
#define CORE_BUF_30 0x30
#define CORE_BUF_38 0x38
#define IOCSR_IPI_SEND 0x40
#define IOCSR_MAIL_SEND 0x48
#define IOCSR_ANY_SEND 0x158
/* IPI system memory address */
#define IPI_SYSTEM_MEM 0x1fe01000
#define MAX_IPI_CORE_NUM 4
#define MAX_IPI_MBX_NUM 4
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
typedef struct IPICore {
uint32_t status;
uint32_t en;
uint32_t set;
uint32_t clear;
/* 64bit buf divide into 2 32bit buf */
uint32_t buf[MAX_IPI_MBX_NUM * 2];
qemu_irq irq;
} IPICore;
struct LoongArchIPI {
SysBusDevice parent_obj;
MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM];
};
#endif