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target/riscv/tcg: decouple profile enablement from user prop
We have code in riscv_cpu_add_profiles() to enable a profile right away
in case a CPU chose the profile during its cpu_init(). But we're using
the user callback option to do so, setting profile->user_set.
Create a new helper that does all the grunt work to enable/disable a
given profile. Use this new helper in the cases where we want a CPU to
be compatible to a certain profile, leaving the user callback to be used
exclusively by users.
Fixes: fba92a92e3 ("target/riscv: add 'rva22u64' CPU")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Message-ID: <20250528184407.1451983-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
Alistair Francis
parent
a429f9304d
commit
f655704c3d
1 changed files with 67 additions and 60 deletions
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@ -1166,6 +1166,70 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
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return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
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}
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}
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static void riscv_cpu_set_profile(RISCVCPU *cpu,
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RISCVCPUProfile *profile,
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bool enabled)
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{
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int i, ext_offset;
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if (profile->u_parent != NULL) {
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riscv_cpu_set_profile(cpu, profile->u_parent, enabled);
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}
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if (profile->s_parent != NULL) {
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riscv_cpu_set_profile(cpu, profile->s_parent, enabled);
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}
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profile->enabled = enabled;
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if (profile->enabled) {
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cpu->env.priv_ver = profile->priv_spec;
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#ifndef CONFIG_USER_ONLY
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if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
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object_property_set_bool(OBJECT(cpu), "mmu", true, NULL);
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const char *satp_prop = satp_mode_str(profile->satp_mode,
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riscv_cpu_is_32bit(cpu));
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object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL);
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}
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#endif
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}
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for (i = 0; misa_bits[i] != 0; i++) {
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uint32_t bit = misa_bits[i];
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if (!(profile->misa_ext & bit)) {
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continue;
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}
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if (bit == RVI && !profile->enabled) {
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/*
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* Disabling profiles will not disable the base
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* ISA RV64I.
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*/
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continue;
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}
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cpu_misa_ext_add_user_opt(bit, profile->enabled);
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riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
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}
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for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
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ext_offset = profile->ext_offsets[i];
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if (profile->enabled) {
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if (cpu_cfg_offset_is_named_feat(ext_offset)) {
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riscv_cpu_enable_named_feat(cpu, ext_offset);
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}
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cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset);
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}
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cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
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isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
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}
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}
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/*
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/*
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* We'll get here via the following path:
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* We'll get here via the following path:
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*
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*
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@ -1332,7 +1396,6 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
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RISCVCPUProfile *profile = opaque;
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RISCVCPUProfile *profile = opaque;
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RISCVCPU *cpu = RISCV_CPU(obj);
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RISCVCPU *cpu = RISCV_CPU(obj);
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bool value;
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bool value;
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int i, ext_offset;
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if (riscv_cpu_is_vendor(obj)) {
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if (riscv_cpu_is_vendor(obj)) {
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error_setg(errp, "Profile %s is not available for vendor CPUs",
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error_setg(errp, "Profile %s is not available for vendor CPUs",
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@ -1351,64 +1414,8 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
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}
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}
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profile->user_set = true;
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profile->user_set = true;
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profile->enabled = value;
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if (profile->u_parent != NULL) {
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riscv_cpu_set_profile(cpu, profile, value);
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object_property_set_bool(obj, profile->u_parent->name,
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profile->enabled, NULL);
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}
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if (profile->s_parent != NULL) {
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object_property_set_bool(obj, profile->s_parent->name,
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profile->enabled, NULL);
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}
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if (profile->enabled) {
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cpu->env.priv_ver = profile->priv_spec;
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#ifndef CONFIG_USER_ONLY
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if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
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object_property_set_bool(obj, "mmu", true, NULL);
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const char *satp_prop = satp_mode_str(profile->satp_mode,
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riscv_cpu_is_32bit(cpu));
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object_property_set_bool(obj, satp_prop, true, NULL);
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}
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#endif
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}
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for (i = 0; misa_bits[i] != 0; i++) {
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uint32_t bit = misa_bits[i];
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if (!(profile->misa_ext & bit)) {
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continue;
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}
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if (bit == RVI && !profile->enabled) {
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/*
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* Disabling profiles will not disable the base
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* ISA RV64I.
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*/
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continue;
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}
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cpu_misa_ext_add_user_opt(bit, profile->enabled);
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riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
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}
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for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
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ext_offset = profile->ext_offsets[i];
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if (profile->enabled) {
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if (cpu_cfg_offset_is_named_feat(ext_offset)) {
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riscv_cpu_enable_named_feat(cpu, ext_offset);
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}
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cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset);
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}
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cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
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isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
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}
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}
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}
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static void cpu_get_profile(Object *obj, Visitor *v, const char *name,
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static void cpu_get_profile(Object *obj, Visitor *v, const char *name,
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@ -1423,7 +1430,7 @@ static void cpu_get_profile(Object *obj, Visitor *v, const char *name,
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static void riscv_cpu_add_profiles(Object *cpu_obj)
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static void riscv_cpu_add_profiles(Object *cpu_obj)
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{
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{
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for (int i = 0; riscv_profiles[i] != NULL; i++) {
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for (int i = 0; riscv_profiles[i] != NULL; i++) {
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const RISCVCPUProfile *profile = riscv_profiles[i];
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RISCVCPUProfile *profile = riscv_profiles[i];
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object_property_add(cpu_obj, profile->name, "bool",
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object_property_add(cpu_obj, profile->name, "bool",
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cpu_get_profile, cpu_set_profile,
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cpu_get_profile, cpu_set_profile,
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@ -1435,7 +1442,7 @@ static void riscv_cpu_add_profiles(Object *cpu_obj)
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* case.
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* case.
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*/
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*/
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if (profile->enabled) {
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if (profile->enabled) {
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object_property_set_bool(cpu_obj, profile->name, true, NULL);
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riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true);
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}
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}
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}
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}
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}
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}
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