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target-arm queue:

Browse source 
* hw/arm/iotkit.c: fix minor memory leak
  * softfloat: fix wrong-exception-flags bug for multiply-add corner case
  * arm: isolate and clean up DTB generation
  * implement Arm v8.1-Atomics extension
  * Fix some bugs and missing instructions in the v8.2-FP16 extension
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging

target-arm queue:
 * hw/arm/iotkit.c: fix minor memory leak
 * softfloat: fix wrong-exception-flags bug for multiply-add corner case
 * arm: isolate and clean up DTB generation
 * implement Arm v8.1-Atomics extension
 * Fix some bugs and missing instructions in the v8.2-FP16 extension

# gpg: Signature made Thu 10 May 2018 18:44:34 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits)
  target/arm: Clear SVE high bits for FMOV
  target/arm: Fix float16 to/from int16
  target/arm: Implement vector shifted FCVT for fp16
  target/arm: Implement vector shifted SCVF/UCVF for fp16
  target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only
  target/arm: Implement CAS and CASP
  target/arm: Fill in disas_ldst_atomic
  target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode
  target/riscv: Use new atomic min/max expanders
  tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add
  tcg: Introduce atomic helpers for integer min/max
  target/xtensa: Use new min/max expanders
  target/arm: Use new min/max expanders
  tcg: Introduce helpers for integer min/max
  atomic.h: Work around gcc spurious "unused value" warning
  make sure that we aren't overwriting mc->get_hotplug_handler by accident
  arm/boot: split load_dtb() from arm_load_kernel()
  platform-bus-device: use device plug callback instead of machine_done notifier
  pc: simplify MachineClass::get_hotplug_handler handling
  softfloat: Handle default NaN mode after pickNaNMulAdd, not before
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	target/riscv/translate.c
This commit is contained in:
Peter Maydell 2018-05-11 17:41:54 +01:00
commit f5583c527f
33 changed files with 934 additions and 504 deletions
Download patch file Download diff file Expand all files Collapse all files

72
target/riscv/translate.c
View file

@ -716,7 +716,6 @@ static void gen_atomic(DisasContext *ctx, uint32_t opc,
TCGv src1, src2, dat;
TCGLabel *l1, *l2;
TCGMemOp mop;
TCGCond cond;
bool aq, rl;
/* Extract the size of the atomic operation. */
@ -814,60 +813,29 @@ static void gen_atomic(DisasContext *ctx, uint32_t opc,
tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(rd, src2);
break;
case OPC_RISC_AMOMIN:
cond = TCG_COND_LT;
goto do_minmax;
case OPC_RISC_AMOMAX:
cond = TCG_COND_GT;
goto do_minmax;
case OPC_RISC_AMOMINU:
cond = TCG_COND_LTU;
goto do_minmax;
case OPC_RISC_AMOMAXU:
cond = TCG_COND_GTU;
goto do_minmax;
do_minmax:
/* Handle the RL barrier. The AQ barrier is handled along the
parallel path by the SC atomic cmpxchg. On the serial path,
of course, barriers do not matter. */
if (rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
l1 = gen_new_label();
gen_set_label(l1);
} else {
l1 = NULL;
}
gen_get_gpr(src1, rs1);
gen_get_gpr(src2, rs2);
if ((mop & MO_SSIZE) == MO_SL) {
/* Sign-extend the register comparison input. */
tcg_gen_ext32s_tl(src2, src2);
}
dat = tcg_temp_local_new();
tcg_gen_qemu_ld_tl(dat, src1, ctx->mem_idx, mop);
tcg_gen_movcond_tl(cond, src2, dat, src2, dat, src2);
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
/* Parallel context. Make this operation atomic by verifying
that the memory didn't change while we computed the result. */
tcg_gen_atomic_cmpxchg_tl(src2, src1, dat, src2, ctx->mem_idx, mop);
/* If the cmpxchg failed, retry. */
/* ??? There is an assumption here that this will eventually
succeed, such that we don't live-lock. This is not unlike
a similar loop that the compiler would generate for e.g.
__atomic_fetch_and_xor, so don't worry about it. */
tcg_gen_brcond_tl(TCG_COND_NE, dat, src2, l1);
} else {
/* Serial context. Directly store the result. */
tcg_gen_qemu_st_tl(src2, src1, ctx->mem_idx, mop);
}
gen_set_gpr(rd, dat);
tcg_temp_free(dat);
tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(rd, src2);
break;
case OPC_RISC_AMOMAX:
gen_get_gpr(src1, rs1);
gen_get_gpr(src2, rs2);
tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(rd, src2);
break;
case OPC_RISC_AMOMINU:
gen_get_gpr(src1, rs1);
gen_get_gpr(src2, rs2);
tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(rd, src2);
break;
case OPC_RISC_AMOMAXU:
gen_get_gpr(src1, rs1);
gen_get_gpr(src2, rs2);
tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(rd, src2);
break;
default: