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QOM boilerplate cleanup

Browse source 
Documentation build fix:
 * memory: Remove kernel-doc comment marker (Eduardo Habkost)
 
 QOM cleanups:
 * Rename QOM macros for consistency between
   TYPE_* and type checking constants (Eduardo Habkost)
 
 QOM new macros:
 * OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé)
 * DECLARE_*_CHECKER macros (Eduardo Habkost)
 
 Automated QOM boilerplate changes:
 * Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost
 * Automated changes to use OBJECT_DECLARE* (Eduardo Habkost)
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Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

QOM boilerplate cleanup

Documentation build fix:
* memory: Remove kernel-doc comment marker (Eduardo Habkost)

QOM cleanups:
* Rename QOM macros for consistency between
  TYPE_* and type checking constants (Eduardo Habkost)

QOM new macros:
* OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé)
* DECLARE_*_CHECKER macros (Eduardo Habkost)

Automated QOM boilerplate changes:
* Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost
* Automated changes to use OBJECT_DECLARE* (Eduardo Habkost)

# gpg: Signature made Thu 10 Sep 2020 19:17:49 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (33 commits)
  virtio-vga: Use typedef name for instance_size
  vhost-user-vga: Use typedef name for instance_size
  xilinx_axienet: Use typedef name for instance_size
  lpc_ich9: Use typedef name for instance_size
  omap_intc: Use typedef name for instance_size
  xilinx_axidma: Use typedef name for instance_size
  tusb6010: Rename TUSB to TUSB6010
  pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312
  vfio: Rename PCI_VFIO to VFIO_PCI
  usb: Rename USB_SERIAL_DEV to USB_SERIAL
  sabre: Rename SABRE_DEVICE to SABRE
  rs6000_mc: Rename RS6000MC_DEVICE to RS6000MC
  filter-rewriter: Rename FILTER_COLO_REWRITER to FILTER_REWRITER
  esp: Rename ESP_STATE to ESP
  ahci: Rename ICH_AHCI to ICH9_AHCI
  vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENID
  vfio: Rename VFIO_AP_DEVICE_TYPE to TYPE_VFIO_AP_DEVICE
  dev-smartcard-reader: Rename CCID_DEV_NAME to TYPE_USB_CCID_DEV
  ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICE
  gpex: Fix type checking function name
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-09-11 19:26:51 +01:00
commit f4ef8c9cc1
827 changed files with 7851 additions and 4406 deletions
Download patch file Download diff file Expand all files Collapse all files

10
hw/timer/altera_timer.c
View file

@ -26,6 +26,7 @@
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
#define R_STATUS 0
#define R_CONTROL 1
@ -44,17 +45,18 @@
#define CONTROL_STOP 0x0008
#define TYPE_ALTERA_TIMER "ALTR.timer"
#define ALTERA_TIMER(obj) \
OBJECT_CHECK(AlteraTimer, (obj), TYPE_ALTERA_TIMER)
typedef struct AlteraTimer AlteraTimer;
DECLARE_INSTANCE_CHECKER(AlteraTimer, ALTERA_TIMER,
TYPE_ALTERA_TIMER)
typedef struct AlteraTimer {
struct AlteraTimer {
SysBusDevice busdev;
MemoryRegion mmio;
qemu_irq irq;
uint32_t freq_hz;
ptimer_state *ptimer;
uint32_t regs[R_MAX];
} AlteraTimer;
};
static int timer_irq_state(AlteraTimer *t)
{

18
hw/timer/arm_timer.c
View file

@ -16,6 +16,7 @@
#include "hw/qdev-properties.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "qom/object.h"
/* Common timer implementation. */
@ -190,9 +191,11 @@ static arm_timer_state *arm_timer_init(uint32_t freq)
*/
#define TYPE_SP804 "sp804"
#define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804)
typedef struct SP804State SP804State;
DECLARE_INSTANCE_CHECKER(SP804State, SP804,
TYPE_SP804)
typedef struct SP804State {
struct SP804State {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -200,7 +203,7 @@ typedef struct SP804State {
uint32_t freq0, freq1;
int level[2];
qemu_irq irq;
} SP804State;
};
static const uint8_t sp804_ids[] = {
/* Timer ID */
@ -310,15 +313,16 @@ static void sp804_realize(DeviceState *dev, Error **errp)
/* Integrator/CP timer module. */
#define TYPE_INTEGRATOR_PIT "integrator_pit"
#define INTEGRATOR_PIT(obj) \
OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT)
typedef struct icp_pit_state icp_pit_state;
DECLARE_INSTANCE_CHECKER(icp_pit_state, INTEGRATOR_PIT,
TYPE_INTEGRATOR_PIT)
typedef struct {
struct icp_pit_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
arm_timer_state *timer[3];
} icp_pit_state;
};
static uint64_t icp_pit_read(void *opaque, hwaddr offset,
unsigned size)

10
hw/timer/cadence_ttc.c
View file

@ -22,6 +22,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "qom/object.h"
#ifdef CADENCE_TTC_ERR_DEBUG
#define DB_PRINT(...) do { \
@ -69,15 +70,16 @@ typedef struct {
} CadenceTimerState;
#define TYPE_CADENCE_TTC "cadence_ttc"
#define CADENCE_TTC(obj) \
OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC)
typedef struct CadenceTTCState CadenceTTCState;
DECLARE_INSTANCE_CHECKER(CadenceTTCState, CADENCE_TTC,
TYPE_CADENCE_TTC)
typedef struct CadenceTTCState {
struct CadenceTTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
CadenceTimerState timer[3];
} CadenceTTCState;
};
static void cadence_timer_update(CadenceTimerState *s)
{

10
hw/timer/etraxfs_timer.c
View file

@ -30,6 +30,7 @@
#include "qemu/timer.h"
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "qom/object.h"
#define D(x)
@ -48,10 +49,11 @@
#define R_MASKED_INTR 0x54
#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
#define ETRAX_TIMER(obj) \
OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
typedef struct ETRAXTimerState ETRAXTimerState;
DECLARE_INSTANCE_CHECKER(ETRAXTimerState, ETRAX_TIMER,
TYPE_ETRAX_FS_TIMER)
typedef struct ETRAXTimerState {
struct ETRAXTimerState {
SysBusDevice parent_obj;
MemoryRegion mmio;
@ -79,7 +81,7 @@ typedef struct ETRAXTimerState {
uint32_t rw_ack_intr;
uint32_t r_intr;
uint32_t r_masked_intr;
} ETRAXTimerState;
};
static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)

10
hw/timer/exynos4210_mct.c
View file

@ -62,6 +62,7 @@
#include "hw/arm/exynos4210.h"
#include "hw/irq.h"
#include "qom/object.h"
//#define DEBUG_MCT
@ -242,10 +243,11 @@ typedef struct {
} Exynos4210MCTLT;
#define TYPE_EXYNOS4210_MCT "exynos4210.mct"
#define EXYNOS4210_MCT(obj) \
OBJECT_CHECK(Exynos4210MCTState, (obj), TYPE_EXYNOS4210_MCT)
typedef struct Exynos4210MCTState Exynos4210MCTState;
DECLARE_INSTANCE_CHECKER(Exynos4210MCTState, EXYNOS4210_MCT,
TYPE_EXYNOS4210_MCT)
typedef struct Exynos4210MCTState {
struct Exynos4210MCTState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -257,7 +259,7 @@ typedef struct Exynos4210MCTState {
Exynos4210MCTGT g_timer;
uint32_t freq; /* all timers tick frequency, TCLK */
} Exynos4210MCTState;
};
/*** VMState ***/
static const VMStateDescription vmstate_tick_timer = {

10
hw/timer/exynos4210_pwm.c
View file

@ -30,6 +30,7 @@
#include "hw/arm/exynos4210.h"
#include "hw/irq.h"
#include "qom/object.h"
//#define DEBUG_PWM
@ -102,10 +103,11 @@ typedef struct {
} Exynos4210PWM;
#define TYPE_EXYNOS4210_PWM "exynos4210.pwm"
#define EXYNOS4210_PWM(obj) \
OBJECT_CHECK(Exynos4210PWMState, (obj), TYPE_EXYNOS4210_PWM)
typedef struct Exynos4210PWMState Exynos4210PWMState;
DECLARE_INSTANCE_CHECKER(Exynos4210PWMState, EXYNOS4210_PWM,
TYPE_EXYNOS4210_PWM)
typedef struct Exynos4210PWMState {
struct Exynos4210PWMState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -116,7 +118,7 @@ typedef struct Exynos4210PWMState {
Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM];
} Exynos4210PWMState;
};
/*** VMState ***/
static const VMStateDescription vmstate_exynos4210_pwm = {

7
hw/timer/grlib_gptimer.c
View file

@ -32,6 +32,7 @@
#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"
#define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */
#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */
@ -55,11 +56,11 @@
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE 0x10
#define GRLIB_GPTIMER(obj) \
OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)
typedef struct GPTimerUnit GPTimerUnit;
DECLARE_INSTANCE_CHECKER(GPTimerUnit, GRLIB_GPTIMER,
TYPE_GRLIB_GPTIMER)
typedef struct GPTimer GPTimer;
typedef struct GPTimerUnit GPTimerUnit;
struct GPTimer {
struct ptimer_state *ptimer;

9
hw/timer/hpet.c
View file

@ -37,6 +37,7 @@
#include "migration/vmstate.h"
#include "hw/timer/i8254.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
//#define HPET_DEBUG
#ifdef HPET_DEBUG
@ -47,7 +48,9 @@
#define HPET_MSI_SUPPORT 0
#define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET)
typedef struct HPETState HPETState;
DECLARE_INSTANCE_CHECKER(HPETState, HPET,
TYPE_HPET)
struct HPETState;
typedef struct HPETTimer { /* timers */
@ -65,7 +68,7 @@ typedef struct HPETTimer { /* timers */
*/
} HPETTimer;
typedef struct HPETState {
struct HPETState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -87,7 +90,7 @@ typedef struct HPETState {
uint64_t isr; /* interrupt status reg */
uint64_t hpet_counter; /* main counter */
uint8_t hpet_id; /* instance id */
} HPETState;
};
static uint32_t hpet_in_legacy_mode(HPETState *s)
{

10
hw/timer/i8254.c
View file

@ -28,6 +28,7 @@
#include "qemu/timer.h"
#include "hw/timer/i8254.h"
#include "hw/timer/i8254_internal.h"
#include "qom/object.h"
//#define DEBUG_PIT
@ -36,14 +37,15 @@
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4
#define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
#define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)
typedef struct PITClass PITClass;
DECLARE_CLASS_CHECKERS(PITClass, PIT,
TYPE_I8254)
typedef struct PITClass {
struct PITClass {
PITCommonClass parent_class;
DeviceRealize parent_realize;
} PITClass;
};
static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);

6
hw/timer/lm32_timer.c
View file

@ -31,6 +31,7 @@
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
#define DEFAULT_FREQUENCY (50*1000000)
@ -55,7 +56,9 @@ enum {
};
#define TYPE_LM32_TIMER "lm32-timer"
#define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
typedef struct LM32TimerState LM32TimerState;
DECLARE_INSTANCE_CHECKER(LM32TimerState, LM32_TIMER,
TYPE_LM32_TIMER)
struct LM32TimerState {
SysBusDevice parent_obj;
@ -69,7 +72,6 @@ struct LM32TimerState {
uint32_t regs[R_MAX];
};
typedef struct LM32TimerState LM32TimerState;
static void timer_update_irq(LM32TimerState *s)
{

7
hw/timer/milkymist-sysctl.c
View file

@ -32,6 +32,7 @@
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
enum {
CTRL_ENABLE = (1<<0),
@ -62,8 +63,9 @@ enum {
};
#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
#define MILKYMIST_SYSCTL(obj) \
OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
typedef struct MilkymistSysctlState MilkymistSysctlState;
DECLARE_INSTANCE_CHECKER(MilkymistSysctlState, MILKYMIST_SYSCTL,
TYPE_MILKYMIST_SYSCTL)
struct MilkymistSysctlState {
SysBusDevice parent_obj;
@ -84,7 +86,6 @@ struct MilkymistSysctlState {
qemu_irq timer0_irq;
qemu_irq timer1_irq;
};
typedef struct MilkymistSysctlState MilkymistSysctlState;
static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
{

9
hw/timer/puv3_ost.c
View file

@ -15,15 +15,18 @@
#include "hw/ptimer.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "qom/object.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#define TYPE_PUV3_OST "puv3_ost"
#define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
typedef struct PUV3OSTState PUV3OSTState;
DECLARE_INSTANCE_CHECKER(PUV3OSTState, PUV3_OST,
TYPE_PUV3_OST)
/* puv3 ostimer implementation. */
typedef struct PUV3OSTState {
struct PUV3OSTState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -34,7 +37,7 @@ typedef struct PUV3OSTState {
uint32_t reg_OSCR;
uint32_t reg_OSSR;
uint32_t reg_OIER;
} PUV3OSTState;
};
static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
unsigned size)

7
hw/timer/pxa2xx_timer.c
View file

@ -17,6 +17,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
#define OSMR0 0x00
#define OSMR1 0x04
@ -66,10 +67,10 @@ static int pxa2xx_timer4_freq[8] = {
};
#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
#define PXA2XX_TIMER(obj) \
OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
DECLARE_INSTANCE_CHECKER(PXA2xxTimerInfo, PXA2XX_TIMER,
TYPE_PXA2XX_TIMER)
typedef struct {
uint32_t value;

10
hw/timer/slavio_timer.c
View file

@ -31,6 +31,7 @@
#include "migration/vmstate.h"
#include "trace.h"
#include "qemu/module.h"
#include "qom/object.h"
/*
* Registers of hardware timer in sun4m.
@ -59,16 +60,17 @@ typedef struct CPUTimerState {
} CPUTimerState;
#define TYPE_SLAVIO_TIMER "slavio_timer"
#define SLAVIO_TIMER(obj) \
OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER)
typedef struct SLAVIO_TIMERState SLAVIO_TIMERState;
DECLARE_INSTANCE_CHECKER(SLAVIO_TIMERState, SLAVIO_TIMER,
TYPE_SLAVIO_TIMER)
typedef struct SLAVIO_TIMERState {
struct SLAVIO_TIMERState {
SysBusDevice parent_obj;
uint32_t num_cpus;
uint32_t cputimer_mode;
CPUTimerState cputimer[MAX_CPUS + 1];
} SLAVIO_TIMERState;
};
typedef struct TimerContext {
MemoryRegion iomem;

5
hw/timer/xilinx_timer.c
View file

@ -29,6 +29,7 @@
#include "hw/qdev-properties.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
#define D(x)
@ -61,8 +62,8 @@ struct xlx_timer
};
#define TYPE_XILINX_TIMER "xlnx.xps-timer"
#define XILINX_TIMER(obj) \
OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
TYPE_XILINX_TIMER)
struct timerblock
{