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target/openrisc: Support non-busy idle state using PMR SPR

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The OpenRISC architecture has the Power Management Register (PMR)
special purpose register to manage cpu power states.  The interesting
modes are:

 * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
 * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
 * Suspend Model (SUME) - Stop cpu and all units - wake on reset

The linux kernel will set DME when idle.

This patch implements the PMR SPR and halts the qemu cpu when there is a
change to DME or SME.  This means that openrisc qemu in no longer peggs
a host cpu at 100%.

In order for this to work we need to kick the CPU when timers are
expired.  Update the cpu timer to kick the cpu upon each timer event.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2017-04-24 06:07:42 +09:00
parent 48a1b62baa
commit f4d1414a93
6 changed files with 29 additions and 1 deletions
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10
target/openrisc/cpu.h
View file

@ -140,6 +140,15 @@ enum {
IMMUCFGR_HTR = (1 << 11),
};
/* Power management register */
enum {
PMR_SDF = (15 << 0),
PMR_DME = (1 << 4),
PMR_SME = (1 << 5),
PMR_DCGE = (1 << 6),
PMR_SUME = (1 << 7),
};
/* Float point control status register */
enum {
FPCSR_FPEE = 1,
@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState {
uint32_t immucfgr; /* IMMU configure register */
uint32_t esr; /* Exception supervisor register */
uint32_t evbar; /* Exception vector base address register */
uint32_t pmr; /* Power Management Register */
uint32_t fpcsr; /* Float register */
float_status fp_status;