motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 00:03:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/intc/loongarch_pch: Merge three memory region into one

Browse source 
Since memory region iomem supports memory access size with 1/2/4/8,
it can be used for memory region iomem8 and iomem32_high. Now remove
memory region iomem8 and iomem32_high, merge them into iomem together.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023754.1877445-5-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Bibo Mao 2025-05-07 10:37:54 +08:00 • committed by Song Gao
parent 2493ff01dc
commit f4881c67ba
3 changed files with 1 additions and 73 deletions
Download patch file Download diff file Expand all files Collapse all files

66
hw/intc/loongarch_pch_pic.c
View file

@ -230,34 +230,6 @@ static void loongarch_pch_pic_write(void *opaque, hwaddr addr,
}
}
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
unsigned size)
{
addr += PCH_PIC_INT_STATUS;
return loongarch_pch_pic_read(opaque, addr, size);
}
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
addr += PCH_PIC_INT_STATUS;
loongarch_pch_pic_write(opaque, addr, value, size);
}
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
unsigned size)
{
addr += PCH_PIC_ROUTE_ENTRY;
return loongarch_pch_pic_read(opaque, addr, size);
}
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
addr += PCH_PIC_ROUTE_ENTRY;
loongarch_pch_pic_write(opaque, addr, data, size);
}
static const MemoryRegionOps loongarch_pch_pic_ops = {
.read = loongarch_pch_pic_read,
.write = loongarch_pch_pic_write,
@ -279,34 +251,6 @@ static const MemoryRegionOps loongarch_pch_pic_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps loongarch_pch_pic_reg32_high_ops = {
.read = loongarch_pch_pic_high_readw,
.write = loongarch_pch_pic_high_writew,
.valid = {
.min_access_size = 4,
.max_access_size = 8,
},
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
.read = loongarch_pch_pic_readb,
.write = loongarch_pch_pic_writeb,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void loongarch_pic_reset_hold(Object *obj, ResetType type)
{
LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(obj);
@ -333,16 +277,8 @@ static void loongarch_pic_realize(DeviceState *dev, Error **errp)
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
memory_region_init_io(&s->iomem, OBJECT(dev),
&loongarch_pch_pic_ops,
s, TYPE_LOONGARCH_PIC, 0x100);
memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
s, PCH_PIC_NAME(.reg8), 0x2a0);
memory_region_init_io(&s->iomem32_high, OBJECT(dev),
&loongarch_pch_pic_reg32_high_ops,
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
s, TYPE_LOONGARCH_PIC, VIRT_PCH_REG_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem8);
sysbus_init_mmio(sbd, &s->iomem32_high);
}
static void loongarch_pic_class_init(ObjectClass *klass, const void *data)