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net: Replace TAB indentations with spaces
Replaces TABs with spaces, making sure to have a consistent coding style of 4 space indentations in the net subsystem. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/377 Signed-off-by: Ahmed Abouzied <email@aabouzied.com> Message-Id: <20210614183849.20622-1-email@aabouzied.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [thuth: Fixed mis-aligned indentation in some of the files] Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Ahmed Abouzied
Thomas Huth
parent
e0091133e3
commit
f469150be8
8 changed files with 867 additions and 867 deletions
138
hw/net/ne2000.c
138
hw/net/ne2000.c
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@ -36,89 +36,89 @@
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#define MAX_ETH_FRAME_SIZE 1514
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
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#define EN0_TSR 0x04 /* Transmit status reg RD */
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#define EN0_TPSR 0x04 /* Transmit starting page WR */
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#define EN0_NCR 0x05 /* Number of collision reg RD */
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
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#define EN0_FIFO 0x06 /* FIFO RD */
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
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#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
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#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
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#define EN0_RSR 0x0c /* rx status reg RD */
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#define EN0_RXCR 0x0c /* RX configuration reg WR */
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#define EN0_TXCR 0x0d /* TX configuration reg WR */
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
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#define EN0_DCFG 0x0e /* Data configuration reg WR */
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
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#define EN0_TSR 0x04 /* Transmit status reg RD */
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#define EN0_TPSR 0x04 /* Transmit starting page WR */
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#define EN0_NCR 0x05 /* Number of collision reg RD */
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
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#define EN0_FIFO 0x06 /* FIFO RD */
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
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#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
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#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
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#define EN0_RSR 0x0c /* rx status reg RD */
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#define EN0_RXCR 0x0c /* RX configuration reg WR */
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#define EN0_TXCR 0x0d /* TX configuration reg WR */
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
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#define EN0_DCFG 0x0e /* Data configuration reg WR */
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
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#define EN1_PHYS 0x11
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#define EN1_CURPAG 0x17
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#define EN1_MULT 0x18
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
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#define EN3_CONFIG0 0x33
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#define EN3_CONFIG1 0x34
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#define EN3_CONFIG2 0x35
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#define EN3_CONFIG3 0x36
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#define EN3_CONFIG0 0x33
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#define EN3_CONFIG1 0x34
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#define EN3_CONFIG2 0x35
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#define EN3_CONFIG3 0x36
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */
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#define E8390_START 0x02 /* Start the chip, clear reset */
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#define E8390_TRANS 0x04 /* Transmit a frame */
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#define E8390_RREAD 0x08 /* Remote read */
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#define E8390_RWRITE 0x10 /* Remote write */
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#define E8390_NODMA 0x20 /* Remote DMA */
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#define E8390_PAGE0 0x00 /* Select page chip registers */
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#define E8390_PAGE1 0x40 /* using the two high-order bits */
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */
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#define E8390_START 0x02 /* Start the chip, clear reset */
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#define E8390_TRANS 0x04 /* Transmit a frame */
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#define E8390_RREAD 0x08 /* Remote read */
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#define E8390_RWRITE 0x10 /* Remote write */
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#define E8390_NODMA 0x20 /* Remote DMA */
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#define E8390_PAGE0 0x00 /* Select page chip registers */
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#define E8390_PAGE1 0x40 /* using the two high-order bits */
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */
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#define ENISR_TX 0x02 /* Transmitter, no error */
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */
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#define ENISR_RDC 0x40 /* remote dma complete */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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#define ENISR_RX 0x01 /* Receiver, no error */
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#define ENISR_TX 0x02 /* Transmitter, no error */
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */
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#define ENISR_RDC 0x40 /* remote dma complete */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */
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#define ENRSR_CRC 0x02 /* CRC error */
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#define ENRSR_FAE 0x04 /* frame alignment error */
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#define ENRSR_FO 0x08 /* FIFO overrun */
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#define ENRSR_MPA 0x10 /* missed pkt */
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#define ENRSR_PHY 0x20 /* physical/multicast address */
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
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#define ENRSR_DEF 0x80 /* deferring */
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#define ENRSR_RXOK 0x01 /* Received a good packet */
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#define ENRSR_CRC 0x02 /* CRC error */
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#define ENRSR_FAE 0x04 /* frame alignment error */
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#define ENRSR_FO 0x08 /* FIFO overrun */
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#define ENRSR_MPA 0x10 /* missed pkt */
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#define ENRSR_PHY 0x20 /* physical/multicast address */
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
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#define ENRSR_DEF 0x80 /* deferring */
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
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void ne2000_reset(NE2000State *s)
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@ -425,13 +425,13 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
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ret = 0x43;
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break;
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case EN3_CONFIG0:
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ret = 0; /* 10baseT media */
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ret = 0; /* 10baseT media */
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break;
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case EN3_CONFIG2:
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ret = 0x40; /* 10baseT active */
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ret = 0x40; /* 10baseT active */
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break;
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case EN3_CONFIG3:
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ret = 0x40; /* Full duplex */
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ret = 0x40; /* Full duplex */
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break;
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default:
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ret = 0x00;
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