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target/riscv: Drop tcg_temp_free

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Translators are no longer required to free tcg temporaries.

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-24 20:28:43 -10:00
parent 574f31161e
commit f43442961e
10 changed files with 1 additions and 215 deletions
Download patch file Download diff file Expand all files Collapse all files

24
target/riscv/insn_trans/trans_rvb.c.inc
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@ -64,7 +64,6 @@ static void gen_clzw(TCGv ret, TCGv arg1)
TCGv t = tcg_temp_new();
tcg_gen_shli_tl(t, arg1, 32);
tcg_gen_clzi_tl(ret, t, 32);
tcg_temp_free(t);
}
static bool trans_clz(DisasContext *ctx, arg_clz *a)
@ -161,8 +160,6 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
gen_sbop_mask(t, shamt);
tcg_gen_or_tl(ret, arg1, t);
tcg_temp_free(t);
}
static bool trans_bset(DisasContext *ctx, arg_bset *a)
@ -183,8 +180,6 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
gen_sbop_mask(t, shamt);
tcg_gen_andc_tl(ret, arg1, t);
tcg_temp_free(t);
}
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
@ -205,8 +200,6 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
gen_sbop_mask(t, shamt);
tcg_gen_xor_tl(ret, arg1, t);
tcg_temp_free(t);
}
static bool trans_binv(DisasContext *ctx, arg_binv *a)
@ -252,9 +245,6 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
/* sign-extend 64-bits */
tcg_gen_ext_i32_tl(ret, t1);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
}
static bool trans_ror(DisasContext *ctx, arg_ror *a)
@ -270,8 +260,6 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
tcg_gen_trunc_tl_i32(t1, arg1);
tcg_gen_rotri_i32(t1, t1, shamt);
tcg_gen_ext_i32_tl(ret, t1);
tcg_temp_free_i32(t1);
}
static bool trans_rori(DisasContext *ctx, arg_rori *a)
@ -294,9 +282,6 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
/* sign-extend 64-bits */
tcg_gen_ext_i32_tl(ret, t1);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
}
static bool trans_rol(DisasContext *ctx, arg_rol *a)
@ -340,8 +325,6 @@ static void gen_orc_b(TCGv ret, TCGv source1)
/* Replicate the lsb of each byte across the byte. */
tcg_gen_muli_tl(ret, tmp, 0xff);
tcg_temp_free(tmp);
}
static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
@ -357,8 +340,6 @@ static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
\
tcg_gen_shli_tl(t, arg1, SHAMT); \
tcg_gen_add_tl(ret, t, arg2); \
\
tcg_temp_free(t); \
}
GEN_SHADD(1)
@ -446,8 +427,6 @@ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
\
tcg_gen_shli_tl(t, t, SHAMT); \
tcg_gen_add_tl(ret, t, arg2); \
\
tcg_temp_free(t); \
}
GEN_SHADD_UW(1)
@ -472,7 +451,6 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
TCGv t = tcg_temp_new();
tcg_gen_ext32u_tl(t, arg1);
tcg_gen_add_tl(ret, t, arg2);
tcg_temp_free(t);
}
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
@ -531,7 +509,6 @@ static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
tcg_gen_ext8u_tl(t, src2);
tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
tcg_temp_free(t);
}
static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
@ -540,7 +517,6 @@ static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
tcg_gen_ext16s_tl(t, src2);
tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
tcg_temp_free(t);
}
static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)