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Save state for all CP0 instructions, they may throw a CPU exception.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2622 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-04-06 18:46:01 +00:00
parent 42a10898a8
commit f41c52f170
3 changed files with 45 additions and 16 deletions
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22
target-mips/op.c
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@ -1360,9 +1360,14 @@ void op_mtc0_status (void)
no 64bit addressing implemented. */
val = (int32_t)T0 & 0xF878FF17;
old = env->CP0_Status;
if (!(val & (1 << CP0St_EXL)) &&
!(val & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM) &&
(val & (1 << CP0St_UM)))
env->hflags |= MIPS_HFLAG_UM;
env->CP0_Status = val;
if (loglevel & CPU_LOG_TB_IN_ASM)
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
CALL_FROM_TB1(cpu_mips_update_irq, env);
RETURN();
}
@ -2077,10 +2082,12 @@ void op_set_lladdr (void)
RETURN();
}
void debug_eret (void);
void debug_pre_eret (void);
void debug_post_eret (void);
void op_eret (void)
{
CALL_FROM_TB0(debug_eret);
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_pre_eret);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->PC = env->CP0_ErrorEPC;
env->CP0_Status &= ~(1 << CP0St_ERL);
@ -2093,13 +2100,16 @@ void op_eret (void)
!(env->hflags & MIPS_HFLAG_DM) &&
(env->CP0_Status & (1 << CP0St_UM)))
env->hflags |= MIPS_HFLAG_UM;
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env->CP0_LLAddr = 1;
RETURN();
}
void op_deret (void)
{
CALL_FROM_TB0(debug_eret);
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_pre_eret);
env->PC = env->CP0_DEPC;
env->hflags |= MIPS_HFLAG_DM;
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
@ -2107,6 +2117,8 @@ void op_deret (void)
!(env->hflags & MIPS_HFLAG_DM) &&
(env->CP0_Status & (1 << CP0St_UM)))
env->hflags |= MIPS_HFLAG_UM;
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env->CP0_LLAddr = 1;
RETURN();
}