mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-27 20:33:54 -06:00
linux headers: update against v5.4-rc1
Update the headers against commit:
0f1a7b3fac05 ("timer-of: don't use conditional expression
with mixed 'void' types")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Message-id: 20191003154640.22451-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger
Peter Maydell
parent
3af78db681
commit
f363d039e8
32 changed files with 406 additions and 59 deletions
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@ -259,10 +259,32 @@ struct ethtool_tunable {
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#define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0
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#define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff
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/* Energy Detect Power Down (EDPD) is a feature supported by some PHYs, where
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* the PHY's RX & TX blocks are put into a low-power mode when there is no
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* link detected (typically cable is un-plugged). For RX, only a minimal
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* link-detection is available, and for TX the PHY wakes up to send link pulses
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* to avoid any lock-ups in case the peer PHY may also be running in EDPD mode.
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*
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* Some PHYs may support configuration of the wake-up interval for TX pulses,
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* and some PHYs may support only disabling TX pulses entirely. For the latter
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* a special value is required (ETHTOOL_PHY_EDPD_NO_TX) so that this can be
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* configured from userspace (should the user want it).
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*
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* The interval units for TX wake-up are in milliseconds, since this should
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* cover a reasonable range of intervals:
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* - from 1 millisecond, which does not sound like much of a power-saver
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* - to ~65 seconds which is quite a lot to wait for a link to come up when
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* plugging a cable
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*/
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#define ETHTOOL_PHY_EDPD_DFLT_TX_MSECS 0xffff
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#define ETHTOOL_PHY_EDPD_NO_TX 0xfffe
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#define ETHTOOL_PHY_EDPD_DISABLE 0
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enum phy_tunable_id {
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ETHTOOL_PHY_ID_UNSPEC,
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ETHTOOL_PHY_DOWNSHIFT,
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ETHTOOL_PHY_FAST_LINK_DOWN,
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ETHTOOL_PHY_EDPD,
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/*
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* Add your fresh new phy tunable attribute above and remember to update
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* phy_tunable_strings[] in net/core/ethtool.c
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@ -1483,6 +1505,8 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,
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ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,
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ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,
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ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,
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ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,
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/* must be last entry */
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__ETHTOOL_LINK_MODE_MASK_NBITS
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@ -528,6 +528,7 @@
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#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
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#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
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#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
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#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
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@ -556,6 +557,7 @@
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#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
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#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
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#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
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#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
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@ -589,6 +591,7 @@
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#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
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#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
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#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
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#define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */
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#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */
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#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
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#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */
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@ -661,6 +664,7 @@
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#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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@ -668,6 +672,7 @@
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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@ -709,7 +714,9 @@
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#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
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#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
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#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
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#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
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#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
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#define PCI_EXT_CAP_DSN_SIZEOF 12
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#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
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@ -1049,4 +1056,14 @@
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#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
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#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
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/* Data Link Feature */
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#define PCI_DLF_CAP 0x04 /* Capabilities Register */
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#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
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/* Physical Layer 16.0 GT/s */
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#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
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#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F
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#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
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#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
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#endif /* LINUX_PCI_REGS_H */
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19
include/standard-headers/linux/virtio_fs.h
Normal file
19
include/standard-headers/linux/virtio_fs.h
Normal file
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
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#ifndef _LINUX_VIRTIO_FS_H
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#define _LINUX_VIRTIO_FS_H
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#include "standard-headers/linux/types.h"
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#include "standard-headers/linux/virtio_ids.h"
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#include "standard-headers/linux/virtio_config.h"
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#include "standard-headers/linux/virtio_types.h"
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struct virtio_fs_config {
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/* Filesystem name (UTF-8, not NUL-terminated, padded with NULs) */
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uint8_t tag[36];
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/* Number of request queues */
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uint32_t num_request_queues;
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} QEMU_PACKED;
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#endif /* _LINUX_VIRTIO_FS_H */
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@ -43,6 +43,8 @@
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#define VIRTIO_ID_INPUT 18 /* virtio input */
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#define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */
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#define VIRTIO_ID_CRYPTO 20 /* virtio crypto */
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#define VIRTIO_ID_IOMMU 23 /* virtio IOMMU */
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#define VIRTIO_ID_FS 26 /* virtio filesystem */
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#define VIRTIO_ID_PMEM 27 /* virtio pmem */
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#endif /* _LINUX_VIRTIO_IDS_H */
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165
include/standard-headers/linux/virtio_iommu.h
Normal file
165
include/standard-headers/linux/virtio_iommu.h
Normal file
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@ -0,0 +1,165 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Virtio-iommu definition v0.12
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*
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* Copyright (C) 2019 Arm Ltd.
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*/
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#ifndef _LINUX_VIRTIO_IOMMU_H
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#define _LINUX_VIRTIO_IOMMU_H
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#include "standard-headers/linux/types.h"
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/* Feature bits */
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#define VIRTIO_IOMMU_F_INPUT_RANGE 0
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#define VIRTIO_IOMMU_F_DOMAIN_RANGE 1
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#define VIRTIO_IOMMU_F_MAP_UNMAP 2
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#define VIRTIO_IOMMU_F_BYPASS 3
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#define VIRTIO_IOMMU_F_PROBE 4
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#define VIRTIO_IOMMU_F_MMIO 5
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struct virtio_iommu_range_64 {
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uint64_t start;
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uint64_t end;
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};
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struct virtio_iommu_range_32 {
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uint32_t start;
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uint32_t end;
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};
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struct virtio_iommu_config {
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/* Supported page sizes */
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uint64_t page_size_mask;
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/* Supported IOVA range */
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struct virtio_iommu_range_64 input_range;
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/* Max domain ID size */
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struct virtio_iommu_range_32 domain_range;
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/* Probe buffer size */
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uint32_t probe_size;
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};
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/* Request types */
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#define VIRTIO_IOMMU_T_ATTACH 0x01
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#define VIRTIO_IOMMU_T_DETACH 0x02
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#define VIRTIO_IOMMU_T_MAP 0x03
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#define VIRTIO_IOMMU_T_UNMAP 0x04
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#define VIRTIO_IOMMU_T_PROBE 0x05
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/* Status types */
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#define VIRTIO_IOMMU_S_OK 0x00
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#define VIRTIO_IOMMU_S_IOERR 0x01
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#define VIRTIO_IOMMU_S_UNSUPP 0x02
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#define VIRTIO_IOMMU_S_DEVERR 0x03
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#define VIRTIO_IOMMU_S_INVAL 0x04
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#define VIRTIO_IOMMU_S_RANGE 0x05
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#define VIRTIO_IOMMU_S_NOENT 0x06
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#define VIRTIO_IOMMU_S_FAULT 0x07
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#define VIRTIO_IOMMU_S_NOMEM 0x08
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struct virtio_iommu_req_head {
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uint8_t type;
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uint8_t reserved[3];
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};
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struct virtio_iommu_req_tail {
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uint8_t status;
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uint8_t reserved[3];
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};
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struct virtio_iommu_req_attach {
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struct virtio_iommu_req_head head;
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uint32_t domain;
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uint32_t endpoint;
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uint8_t reserved[8];
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struct virtio_iommu_req_tail tail;
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};
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struct virtio_iommu_req_detach {
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struct virtio_iommu_req_head head;
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uint32_t domain;
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uint32_t endpoint;
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uint8_t reserved[8];
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struct virtio_iommu_req_tail tail;
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};
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#define VIRTIO_IOMMU_MAP_F_READ (1 << 0)
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#define VIRTIO_IOMMU_MAP_F_WRITE (1 << 1)
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#define VIRTIO_IOMMU_MAP_F_MMIO (1 << 2)
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#define VIRTIO_IOMMU_MAP_F_MASK (VIRTIO_IOMMU_MAP_F_READ | \
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VIRTIO_IOMMU_MAP_F_WRITE | \
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VIRTIO_IOMMU_MAP_F_MMIO)
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struct virtio_iommu_req_map {
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struct virtio_iommu_req_head head;
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uint32_t domain;
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uint64_t virt_start;
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uint64_t virt_end;
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uint64_t phys_start;
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uint32_t flags;
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struct virtio_iommu_req_tail tail;
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};
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struct virtio_iommu_req_unmap {
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struct virtio_iommu_req_head head;
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uint32_t domain;
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uint64_t virt_start;
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uint64_t virt_end;
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uint8_t reserved[4];
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struct virtio_iommu_req_tail tail;
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};
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#define VIRTIO_IOMMU_PROBE_T_NONE 0
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#define VIRTIO_IOMMU_PROBE_T_RESV_MEM 1
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#define VIRTIO_IOMMU_PROBE_T_MASK 0xfff
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struct virtio_iommu_probe_property {
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uint16_t type;
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uint16_t length;
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};
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#define VIRTIO_IOMMU_RESV_MEM_T_RESERVED 0
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#define VIRTIO_IOMMU_RESV_MEM_T_MSI 1
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struct virtio_iommu_probe_resv_mem {
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struct virtio_iommu_probe_property head;
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uint8_t subtype;
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uint8_t reserved[3];
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uint64_t start;
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uint64_t end;
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};
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struct virtio_iommu_req_probe {
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struct virtio_iommu_req_head head;
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uint32_t endpoint;
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uint8_t reserved[64];
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uint8_t properties[];
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/*
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* Tail follows the variable-length properties array. No padding,
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* property lengths are all aligned on 8 bytes.
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*/
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};
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/* Fault types */
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#define VIRTIO_IOMMU_FAULT_R_UNKNOWN 0
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#define VIRTIO_IOMMU_FAULT_R_DOMAIN 1
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#define VIRTIO_IOMMU_FAULT_R_MAPPING 2
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#define VIRTIO_IOMMU_FAULT_F_READ (1 << 0)
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#define VIRTIO_IOMMU_FAULT_F_WRITE (1 << 1)
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#define VIRTIO_IOMMU_FAULT_F_EXEC (1 << 2)
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#define VIRTIO_IOMMU_FAULT_F_ADDRESS (1 << 8)
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struct virtio_iommu_fault {
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uint8_t reason;
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uint8_t reserved[3];
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uint32_t flags;
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uint32_t endpoint;
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uint8_t reserved2[4];
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uint64_t address;
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};
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#endif
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause */
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/*
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* Definitions for virtio-pmem devices.
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*
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@ -7,8 +7,8 @@
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* Author(s): Pankaj Gupta <pagupta@redhat.com>
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*/
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#ifndef _UAPI_LINUX_VIRTIO_PMEM_H
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#define _UAPI_LINUX_VIRTIO_PMEM_H
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#ifndef _LINUX_VIRTIO_PMEM_H
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#define _LINUX_VIRTIO_PMEM_H
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#include "standard-headers/linux/types.h"
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#include "standard-headers/linux/virtio_ids.h"
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