mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-09 18:44:58 -06:00
target-arm queue:
* Support M profile derived exceptions on exception entry and exit * Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4) * Implement working i.MX6 SD controller * Various devices preparatory to i.MX7 support * Preparatory patches for SVE emulation * v8M: Fix bug in implementation of 'TT' insn * Give useful error if user tries to use userspace GICv3 with KVM -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJafX+DAAoJEDwlJe0UNgzegGgP/2OepsVnpg++NkBpJdCq0wjC DFaGLpDqaXabv0E5b56flkqBsK6mO2vXoIiWOLF3f25G5pBf5zu7XOEYXWuOIBEP Yr/vl4/yWRZfiNKl6aPC5HwHKN8SWMV+Mp/GtKz0PtHLY+oGl3fBRBu8fbeoOyj9 3x+HB0c5fpAtWrRoS+XrUJfQPdkkZ4c5lDvpxec57cqOzJ8qYZEcFCi7WP3Rglox sQJEls5IXkOVGx35o7k0rIw0qzcV8iCGBsuA+4QAonxE5B0ip6aolPAaq+gf/mLP StX2UJG9JO5tOhaNBexHE/QwLNu2pver8mghIyluirLvisB6kx+dEoa0Zj/7J7or LD9O6pqpSPCCKLSw0xPOl2FqjXzbIYcjgddxrOGvUQgAhdagB2EeRHiCdZ7hQXvm Pg4gAsIAZURPrbj7LaXgDCzM0IP6bZjNR2U+C0ekJDBRJb/NTLcvlmx3MQo3s4ot s/t6FP728tnmMk7ib8w95oo2oSMiPUZBfj2IMYogXgY+pup0OunKwOQL93Lmj4By LJwawcsa/9ctyzF/XvBUHO/n4l0zZi3wLmtVojbxkxtHiFmvv5gQMlyHYM08aTJ1 Vu/V0tiX6+oXoNrJg5e8TAchsS5PmO54Sj/ywMm5Q8FWfBE19KTRl5BatxbMYahU gQQt64esxQQFxxjdSrZY =bokK -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180209' into staging target-arm queue: * Support M profile derived exceptions on exception entry and exit * Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4) * Implement working i.MX6 SD controller * Various devices preparatory to i.MX7 support * Preparatory patches for SVE emulation * v8M: Fix bug in implementation of 'TT' insn * Give useful error if user tries to use userspace GICv3 with KVM # gpg: Signature made Fri 09 Feb 2018 11:01:23 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180209: (30 commits) hw/core/generic-loader: Allow PC to be set on command line target/arm/translate.c: Fix missing 'break' for TT insns target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM target/arm: Add SVE state to TB->FLAGS target/arm: Add ZCR_ELx target/arm: Add SVE to migration state target/arm: Add predicate registers for SVE target/arm: Expand vector registers for SVE hw/arm: Move virt's PSCI DT fixup code to arm/boot.c usb: Add basic code to emulate Chipidea USB IP i.MX: Add implementation of i.MX7 GPR IP block i.MX: Add i.MX7 GPT variant i.MX: Add code to emulate GPCv2 IP block i.MX: Add code to emulate i.MX7 SNVS IP-block i.MX: Add code to emulate i.MX2 watchdog IP block i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC sdhci: Add i.MX specific subtype of SDHCI target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support target/arm: implement SM4 instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
f31cd9e4e2
38 changed files with 2928 additions and 187 deletions
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@ -6,7 +6,7 @@ common-obj-$(CONFIG_XILINX) += xilinx_intc.o
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common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-intc.o
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common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
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common-obj-$(CONFIG_IMX) += imx_avic.o
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common-obj-$(CONFIG_IMX) += imx_avic.o imx_gpcv2.o
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common-obj-$(CONFIG_LM32) += lm32_pic.o
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common-obj-$(CONFIG_REALVIEW) += realview_gic.o
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common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
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@ -503,8 +503,25 @@ static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
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}
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}
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void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
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static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
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bool derived)
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{
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/* Pend an exception, including possibly escalating it to HardFault.
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*
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* This function handles both "normal" pending of interrupts and
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* exceptions, and also derived exceptions (ones which occur as
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* a result of trying to take some other exception).
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*
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* If derived == true, the caller guarantees that we are part way through
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* trying to take an exception (but have not yet called
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* armv7m_nvic_acknowledge_irq() to make it active), and so:
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* - s->vectpending is the "original exception" we were trying to take
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* - irq is the "derived exception"
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* - nvic_exec_prio(s) gives the priority before exception entry
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* Here we handle the prioritization logic which the pseudocode puts
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* in the DerivedLateArrival() function.
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*/
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NVICState *s = (NVICState *)opaque;
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bool banked = exc_is_banked(irq);
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VecInfo *vec;
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@ -514,7 +531,44 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
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vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
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trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
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trace_nvic_set_pending(irq, secure, derived, vec->enabled, vec->prio);
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if (derived) {
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/* Derived exceptions are always synchronous. */
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assert(irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV);
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if (irq == ARMV7M_EXCP_DEBUG &&
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exc_group_prio(s, vec->prio, secure) >= nvic_exec_prio(s)) {
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/* DebugMonitorFault, but its priority is lower than the
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* preempted exception priority: just ignore it.
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*/
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return;
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}
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if (irq == ARMV7M_EXCP_HARD && vec->prio >= s->vectpending_prio) {
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/* If this is a terminal exception (one which means we cannot
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* take the original exception, like a failure to read its
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* vector table entry), then we must take the derived exception.
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* If the derived exception can't take priority over the
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* original exception, then we go into Lockup.
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*
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* For QEMU, we rely on the fact that a derived exception is
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* terminal if and only if it's reported to us as HardFault,
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* which saves having to have an extra argument is_terminal
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* that we'd only use in one place.
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*/
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cpu_abort(&s->cpu->parent_obj,
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"Lockup: can't take terminal derived exception "
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"(original exception priority %d)\n",
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s->vectpending_prio);
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}
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/* We now continue with the same code as for a normal pending
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* exception, which will cause us to pend the derived exception.
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* We'll then take either the original or the derived exception
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* based on which is higher priority by the usual mechanism
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* for selecting the highest priority pending interrupt.
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*/
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}
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if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
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/* If a synchronous exception is pending then it may be
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@ -585,25 +639,31 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
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}
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}
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void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
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{
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do_armv7m_nvic_set_pending(opaque, irq, secure, false);
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}
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void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
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{
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do_armv7m_nvic_set_pending(opaque, irq, secure, true);
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}
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/* Make pending IRQ active. */
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bool armv7m_nvic_acknowledge_irq(void *opaque)
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void armv7m_nvic_acknowledge_irq(void *opaque)
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{
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NVICState *s = (NVICState *)opaque;
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CPUARMState *env = &s->cpu->env;
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const int pending = s->vectpending;
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const int running = nvic_exec_prio(s);
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VecInfo *vec;
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bool targets_secure;
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assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
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if (s->vectpending_is_s_banked) {
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vec = &s->sec_vectors[pending];
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targets_secure = true;
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} else {
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vec = &s->vectors[pending];
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targets_secure = !exc_is_banked(s->vectpending) &&
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exc_targets_secure(s, s->vectpending);
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}
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assert(vec->enabled);
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@ -611,7 +671,7 @@ bool armv7m_nvic_acknowledge_irq(void *opaque)
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assert(s->vectpending_prio < running);
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trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);
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trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
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vec->active = 1;
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vec->pending = 0;
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@ -619,8 +679,28 @@ bool armv7m_nvic_acknowledge_irq(void *opaque)
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write_v7m_exception(env, s->vectpending);
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nvic_irq_update(s);
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}
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return targets_secure;
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void armv7m_nvic_get_pending_irq_info(void *opaque,
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int *pirq, bool *ptargets_secure)
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{
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NVICState *s = (NVICState *)opaque;
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const int pending = s->vectpending;
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bool targets_secure;
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assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
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if (s->vectpending_is_s_banked) {
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targets_secure = true;
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} else {
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targets_secure = !exc_is_banked(pending) &&
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exc_targets_secure(s, pending);
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}
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trace_nvic_get_pending_irq_info(pending, targets_secure);
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*ptargets_secure = targets_secure;
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*pirq = pending;
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}
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int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
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125
hw/intc/imx_gpcv2.c
Normal file
125
hw/intc/imx_gpcv2.c
Normal file
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@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* i.MX7 GPCv2 block emulation code
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/intc/imx_gpcv2.h"
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#include "qemu/log.h"
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
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#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
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#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
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#define PCIE_PHY_SW_Pxx_REQ BIT(1)
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#define MIPI_PHY_SW_Pxx_REQ BIT(0)
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static void imx_gpcv2_reset(DeviceState *dev)
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{
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IMXGPCv2State *s = IMX_GPCV2(dev);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static uint64_t imx_gpcv2_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXGPCv2State *s = opaque;
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return s->regs[offset / sizeof(uint32_t)];
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}
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static void imx_gpcv2_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXGPCv2State *s = opaque;
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const size_t idx = offset / sizeof(uint32_t);
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s->regs[idx] = value;
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/*
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* Real HW will clear those bits once as a way to indicate that
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* power up request is complete
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*/
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if (offset == GPC_PU_PGC_SW_PUP_REQ ||
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offset == GPC_PU_PGC_SW_PDN_REQ) {
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s->regs[idx] &= ~(USB_HSIC_PHY_SW_Pxx_REQ |
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USB_OTG2_PHY_SW_Pxx_REQ |
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USB_OTG1_PHY_SW_Pxx_REQ |
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PCIE_PHY_SW_Pxx_REQ |
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MIPI_PHY_SW_Pxx_REQ);
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}
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}
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static const struct MemoryRegionOps imx_gpcv2_ops = {
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.read = imx_gpcv2_read,
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.write = imx_gpcv2_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx_gpcv2_init(Object *obj)
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{
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SysBusDevice *sd = SYS_BUS_DEVICE(obj);
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IMXGPCv2State *s = IMX_GPCV2(obj);
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memory_region_init_io(&s->iomem,
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obj,
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&imx_gpcv2_ops,
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s,
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TYPE_IMX_GPCV2 ".iomem",
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sizeof(s->regs));
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sysbus_init_mmio(sd, &s->iomem);
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}
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static const VMStateDescription vmstate_imx_gpcv2 = {
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.name = TYPE_IMX_GPCV2,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, IMXGPCv2State, GPC_NUM),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_gpcv2_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = imx_gpcv2_reset;
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dc->vmsd = &vmstate_imx_gpcv2;
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dc->desc = "i.MX GPCv2 Module";
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}
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static const TypeInfo imx_gpcv2_info = {
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.name = TYPE_IMX_GPCV2,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXGPCv2State),
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.instance_init = imx_gpcv2_init,
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.class_init = imx_gpcv2_class_init,
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};
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static void imx_gpcv2_register_type(void)
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{
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type_register_static(&imx_gpcv2_info);
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}
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type_init(imx_gpcv2_register_type)
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@ -177,10 +177,11 @@ nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %
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nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
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nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
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nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
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nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
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nvic_set_pending(int irq, bool secure, bool derived, int en, int prio) "NVIC set pending irq %d secure-bank %d derived %d (enabled: %d priority %d)"
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nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
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nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
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nvic_acknowledge_irq(int irq, int prio, bool targets_secure) "NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)"
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nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
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nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets_secure: %d"
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nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
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nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
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nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
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|
|
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Reference in a new issue