target-mips: correctly handle access to unimplemented CP0 register

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Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.

In pre-R6 the behaviour is not specified, but generating RI exception is not
what the real HW does.

Additionally, remove CP0 Random register as it became reserved in Release 6.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>

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Leon Alrae 2014-07-11 16:11:35 +01:00

parent ba801af429

commit f31b035a9f

1 changed files with 260 additions and 278 deletions

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target-mips/translate.c

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