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target/riscv: Enable uxl field write

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Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:49 +08:00 • committed by Alistair Francis
parent 5a2ae2350e
commit f310df58bd
2 changed files with 25 additions and 6 deletions
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3
target/riscv/cpu_bits.h
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@ -449,6 +449,9 @@ typedef enum {
#define COUNTEREN_IR (1 << 2)
#define COUNTEREN_HPM3 (1 << 3)
/* vsstatus CSR bits */
#define VSSTATUS64_UXL 0x0000000300000000ULL
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1