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target-sparc: Remove helper_ldf_asi, helper_stf_asi
We've now implemented all fp asis inline, except for the no-fault memory reads. The latter can be passed directly to helper_ld_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
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3 changed files with 32 additions and 166 deletions
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@ -2161,154 +2161,6 @@ void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi)
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QT0.low = l;
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}
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void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
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int rd)
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{
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unsigned int i;
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target_ulong val;
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helper_check_align(env, addr, 3);
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addr = asi_address_mask(env, asi, addr);
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switch (asi) {
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case ASI_BLK_P: /* UA2007/JPS1 Block load primary */
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case ASI_BLK_S: /* UA2007/JPS1 Block load secondary */
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case ASI_BLK_PL: /* UA2007/JPS1 Block load primary LE */
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case ASI_BLK_SL: /* UA2007/JPS1 Block load secondary LE */
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if (rd & 7) {
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helper_raise_exception(env, TT_ILL_INSN);
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return;
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}
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helper_check_align(env, addr, 0x3f);
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for (i = 0; i < 8; i++, rd += 2, addr += 8) {
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env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, MO_Q);
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}
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return;
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case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
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case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
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case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
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case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
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case ASI_BLK_AIUP: /* JPS1 Block load primary, user privilege */
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case ASI_BLK_AIUS: /* JPS1 Block load secondary, user privilege */
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case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
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case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
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if (rd & 7) {
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helper_raise_exception(env, TT_ILL_INSN);
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return;
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}
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helper_check_align(env, addr, 0x3f);
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for (i = 0; i < 8; i++, rd += 2, addr += 8) {
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env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, MO_Q);
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}
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return;
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default:
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break;
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}
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switch (size) {
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default:
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case 4:
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val = helper_ld_asi(env, addr, asi, MO_UL);
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if (rd & 1) {
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env->fpr[rd / 2].l.lower = val;
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} else {
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env->fpr[rd / 2].l.upper = val;
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}
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break;
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case 8:
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env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, MO_Q);
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break;
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case 16:
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env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, MO_Q);
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env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, MO_Q);
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break;
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}
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}
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void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
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int rd)
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{
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unsigned int i;
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target_ulong val;
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addr = asi_address_mask(env, asi, addr);
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switch (asi) {
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case ASI_BLK_COMMIT_P: /* UA2007/JPS1 Block store primary (cache flush) */
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case ASI_BLK_COMMIT_S: /* UA2007/JPS1 Block store secondary (cache flush) */
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case ASI_BLK_P: /* UA2007/JPS1 Block store primary */
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case ASI_BLK_S: /* UA2007/JPS1 Block store secondary */
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case ASI_BLK_PL: /* UA2007/JPS1 Block store primary LE */
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case ASI_BLK_SL: /* UA2007/JPS1 Block store secondary LE */
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if (rd & 7) {
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helper_raise_exception(env, TT_ILL_INSN);
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return;
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}
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helper_check_align(env, addr, 0x3f);
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for (i = 0; i < 8; i++, rd += 2, addr += 8) {
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helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, MO_Q);
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}
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return;
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case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
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case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
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case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
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case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
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case ASI_BLK_AIUP: /* JPS1 Block store primary, user privilege */
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case ASI_BLK_AIUS: /* JPS1 Block store secondary, user privilege */
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case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
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case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
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if (rd & 7) {
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helper_raise_exception(env, TT_ILL_INSN);
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return;
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}
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helper_check_align(env, addr, 0x3f);
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for (i = 0; i < 8; i++, rd += 2, addr += 8) {
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helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, MO_Q);
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}
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return;
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case ASI_FL16_P: /* 16-bit floating point load primary */
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case ASI_FL16_S: /* 16-bit floating point load secondary */
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case ASI_FL16_PL: /* 16-bit floating point load primary, LE */
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case ASI_FL16_SL: /* 16-bit floating point load secondary, LE */
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val = env->fpr[rd / 2].l.lower;
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helper_st_asi(env, addr, val, asi & 0x8d, MO_UW);
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return;
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case ASI_FL8_P: /* 8-bit floating point load primary */
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case ASI_FL8_S: /* 8-bit floating point load secondary */
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case ASI_FL8_PL: /* 8-bit floating point load primary, LE */
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case ASI_FL8_SL: /* 8-bit floating point load secondary, LE */
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val = env->fpr[rd / 2].l.lower;
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helper_st_asi(env, addr, val, asi & 0x8d, MO_UB);
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return;
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default:
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helper_check_align(env, addr, 3);
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break;
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}
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switch (size) {
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default:
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case 4:
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if (rd & 1) {
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val = env->fpr[rd / 2].l.lower;
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} else {
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val = env->fpr[rd / 2].l.upper;
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}
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helper_st_asi(env, addr, val, asi, MO_UL);
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break;
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case 8:
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helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, MO_Q);
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break;
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case 16:
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helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, MO_Q);
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helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, MO_Q);
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break;
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}
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}
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target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
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target_ulong val1, target_ulong val2,
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uint32_t asi)
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