target-sparc: Remove helper_ldf_asi, helper_stf_asi

We've now implemented all fp asis inline, except for the no-fault
memory reads.  The latter can be passed directly to helper_ld_asi.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2015-09-08 16:12:46 -07:00
parent ca5ce5723f
commit f2fe396f0f
3 changed files with 32 additions and 166 deletions

View file

@ -2161,154 +2161,6 @@ void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi)
QT0.low = l;
}
void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int rd)
{
unsigned int i;
target_ulong val;
helper_check_align(env, addr, 3);
addr = asi_address_mask(env, asi, addr);
switch (asi) {
case ASI_BLK_P: /* UA2007/JPS1 Block load primary */
case ASI_BLK_S: /* UA2007/JPS1 Block load secondary */
case ASI_BLK_PL: /* UA2007/JPS1 Block load primary LE */
case ASI_BLK_SL: /* UA2007/JPS1 Block load secondary LE */
if (rd & 7) {
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, MO_Q);
}
return;
case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
case ASI_BLK_AIUP: /* JPS1 Block load primary, user privilege */
case ASI_BLK_AIUS: /* JPS1 Block load secondary, user privilege */
case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
if (rd & 7) {
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, MO_Q);
}
return;
default:
break;
}
switch (size) {
default:
case 4:
val = helper_ld_asi(env, addr, asi, MO_UL);
if (rd & 1) {
env->fpr[rd / 2].l.lower = val;
} else {
env->fpr[rd / 2].l.upper = val;
}
break;
case 8:
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, MO_Q);
break;
case 16:
env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, MO_Q);
env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, MO_Q);
break;
}
}
void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int rd)
{
unsigned int i;
target_ulong val;
addr = asi_address_mask(env, asi, addr);
switch (asi) {
case ASI_BLK_COMMIT_P: /* UA2007/JPS1 Block store primary (cache flush) */
case ASI_BLK_COMMIT_S: /* UA2007/JPS1 Block store secondary (cache flush) */
case ASI_BLK_P: /* UA2007/JPS1 Block store primary */
case ASI_BLK_S: /* UA2007/JPS1 Block store secondary */
case ASI_BLK_PL: /* UA2007/JPS1 Block store primary LE */
case ASI_BLK_SL: /* UA2007/JPS1 Block store secondary LE */
if (rd & 7) {
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, MO_Q);
}
return;
case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
case ASI_BLK_AIUP: /* JPS1 Block store primary, user privilege */
case ASI_BLK_AIUS: /* JPS1 Block store secondary, user privilege */
case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
if (rd & 7) {
helper_raise_exception(env, TT_ILL_INSN);
return;
}
helper_check_align(env, addr, 0x3f);
for (i = 0; i < 8; i++, rd += 2, addr += 8) {
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, MO_Q);
}
return;
case ASI_FL16_P: /* 16-bit floating point load primary */
case ASI_FL16_S: /* 16-bit floating point load secondary */
case ASI_FL16_PL: /* 16-bit floating point load primary, LE */
case ASI_FL16_SL: /* 16-bit floating point load secondary, LE */
val = env->fpr[rd / 2].l.lower;
helper_st_asi(env, addr, val, asi & 0x8d, MO_UW);
return;
case ASI_FL8_P: /* 8-bit floating point load primary */
case ASI_FL8_S: /* 8-bit floating point load secondary */
case ASI_FL8_PL: /* 8-bit floating point load primary, LE */
case ASI_FL8_SL: /* 8-bit floating point load secondary, LE */
val = env->fpr[rd / 2].l.lower;
helper_st_asi(env, addr, val, asi & 0x8d, MO_UB);
return;
default:
helper_check_align(env, addr, 3);
break;
}
switch (size) {
default:
case 4:
if (rd & 1) {
val = env->fpr[rd / 2].l.lower;
} else {
val = env->fpr[rd / 2].l.upper;
}
helper_st_asi(env, addr, val, asi, MO_UL);
break;
case 8:
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, MO_Q);
break;
case 16:
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, MO_Q);
helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, MO_Q);
break;
}
}
target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
target_ulong val1, target_ulong val2,
uint32_t asi)