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target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

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Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-2-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rebecca Cran 2021-02-16 15:45:41 -07:00 • committed by Peter Maydell
parent cecc096209
commit f2f68a78b7
4 changed files with 69 additions and 1 deletions
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37
target/arm/helper.c
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@ -4450,6 +4450,24 @@ static const ARMCPRegInfo dit_reginfo = {
.readfn = aa64_dit_read, .writefn = aa64_dit_write
};
static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return env->pstate & PSTATE_SSBS;
}
static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);
}
static const ARMCPRegInfo ssbs_reginfo = {
.name = "SSBS", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,
.type = ARM_CP_NO_RAW, .access = PL0_RW,
.readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write
};
static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
@ -8244,6 +8262,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_dit, cpu)) {
define_one_arm_cp_reg(cpu, &dit_reginfo);
}
if (cpu_isar_feature(aa64_ssbs, cpu)) {
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
define_arm_cp_regs(cpu, vhe_reginfo);
@ -9463,6 +9484,14 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
env->daif |= mask;
if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
env->uncached_cpsr |= CPSR_SSBS;
} else {
env->uncached_cpsr &= ~CPSR_SSBS;
}
}
if (new_mode == ARM_CPU_MODE_HYP) {
env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
env->elr_el[2] = env->regs[15];
@ -9973,6 +10002,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
new_mode |= PSTATE_TCO;
}
if (cpu_isar_feature(aa64_ssbs, cpu)) {
if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
new_mode |= PSTATE_SSBS;
} else {
new_mode &= ~PSTATE_SSBS;
}
}
pstate_write(env, PSTATE_DAIF | new_mode);
env->aarch64 = 1;
aarch64_restore_sp(env, new_el);