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https://github.com/Motorhead1991/qemu.git
synced 2025-08-01 23:03:54 -06:00
Move non-op functions from op_helper.c to helper.c and vice versa.
Rearrange interrupt handling to match other targets. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
8d96d20941
commit
f2bc7e7fa1
5 changed files with 235 additions and 245 deletions
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@ -32,6 +32,7 @@
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//#define DEBUG_MMU
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//#define DEBUG_FEATURES
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//#define DEBUG_PCALL
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typedef struct sparc_def_t sparc_def_t;
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@ -651,6 +652,220 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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}
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#endif
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#ifdef TARGET_SPARC64
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#ifdef DEBUG_PCALL
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static const char * const excp_names[0x50] = {
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[TT_TFAULT] = "Instruction Access Fault",
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[TT_TMISS] = "Instruction Access MMU Miss",
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[TT_CODE_ACCESS] = "Instruction Access Error",
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[TT_ILL_INSN] = "Illegal Instruction",
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[TT_PRIV_INSN] = "Privileged Instruction",
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[TT_NFPU_INSN] = "FPU Disabled",
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[TT_FP_EXCP] = "FPU Exception",
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[TT_TOVF] = "Tag Overflow",
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[TT_CLRWIN] = "Clean Windows",
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[TT_DIV_ZERO] = "Division By Zero",
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[TT_DFAULT] = "Data Access Fault",
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[TT_DMISS] = "Data Access MMU Miss",
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[TT_DATA_ACCESS] = "Data Access Error",
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[TT_DPROT] = "Data Protection Error",
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[TT_UNALIGNED] = "Unaligned Memory Access",
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[TT_PRIV_ACT] = "Privileged Action",
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[TT_EXTINT | 0x1] = "External Interrupt 1",
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[TT_EXTINT | 0x2] = "External Interrupt 2",
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[TT_EXTINT | 0x3] = "External Interrupt 3",
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[TT_EXTINT | 0x4] = "External Interrupt 4",
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[TT_EXTINT | 0x5] = "External Interrupt 5",
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[TT_EXTINT | 0x6] = "External Interrupt 6",
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[TT_EXTINT | 0x7] = "External Interrupt 7",
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[TT_EXTINT | 0x8] = "External Interrupt 8",
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[TT_EXTINT | 0x9] = "External Interrupt 9",
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[TT_EXTINT | 0xa] = "External Interrupt 10",
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[TT_EXTINT | 0xb] = "External Interrupt 11",
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[TT_EXTINT | 0xc] = "External Interrupt 12",
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[TT_EXTINT | 0xd] = "External Interrupt 13",
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[TT_EXTINT | 0xe] = "External Interrupt 14",
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[TT_EXTINT | 0xf] = "External Interrupt 15",
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};
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#endif
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void do_interrupt(CPUState *env)
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{
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int intno = env->exception_index;
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#ifdef DEBUG_PCALL
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if (loglevel & CPU_LOG_INT) {
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static int count;
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const char *name;
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if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
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name = "Unknown";
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else if (intno >= 0x100)
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name = "Trap Instruction";
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else if (intno >= 0xc0)
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name = "Window Fill";
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else if (intno >= 0x80)
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name = "Window Spill";
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else {
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name = excp_names[intno];
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if (!name)
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name = "Unknown";
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}
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fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
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" SP=%016" PRIx64 "\n",
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count, name, intno,
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env->pc,
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env->npc, env->regwptr[6]);
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cpu_dump_state(env, logfile, fprintf, 0);
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#if 0
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{
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int i;
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uint8_t *ptr;
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fprintf(logfile, " code=");
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ptr = (uint8_t *)env->pc;
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for(i = 0; i < 16; i++) {
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fprintf(logfile, " %02x", ldub(ptr + i));
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}
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fprintf(logfile, "\n");
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}
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#endif
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count++;
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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if (env->tl == MAXTL) {
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cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
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env->exception_index);
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return;
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}
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#endif
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env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
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((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
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GET_CWP64(env);
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env->tsptr->tpc = env->pc;
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env->tsptr->tnpc = env->npc;
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env->tsptr->tt = intno;
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change_pstate(PS_PEF | PS_PRIV | PS_AG);
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if (intno == TT_CLRWIN)
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cpu_set_cwp(env, (env->cwp - 1) & (NWINDOWS - 1));
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else if ((intno & 0x1c0) == TT_SPILL)
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cpu_set_cwp(env, (env->cwp - env->cansave - 2) & (NWINDOWS - 1));
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else if ((intno & 0x1c0) == TT_FILL)
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cpu_set_cwp(env, (env->cwp + 1) & (NWINDOWS - 1));
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env->tbr &= ~0x7fffULL;
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env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
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if (env->tl < MAXTL - 1) {
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env->tl++;
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} else {
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env->pstate |= PS_RED;
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if (env->tl != MAXTL)
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env->tl++;
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}
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env->tsptr = &env->ts[env->tl];
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env->pc = env->tbr;
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env->npc = env->pc + 4;
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env->exception_index = 0;
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}
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#else
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#ifdef DEBUG_PCALL
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static const char * const excp_names[0x80] = {
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[TT_TFAULT] = "Instruction Access Fault",
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[TT_ILL_INSN] = "Illegal Instruction",
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[TT_PRIV_INSN] = "Privileged Instruction",
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[TT_NFPU_INSN] = "FPU Disabled",
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[TT_WIN_OVF] = "Window Overflow",
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[TT_WIN_UNF] = "Window Underflow",
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[TT_UNALIGNED] = "Unaligned Memory Access",
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[TT_FP_EXCP] = "FPU Exception",
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[TT_DFAULT] = "Data Access Fault",
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[TT_TOVF] = "Tag Overflow",
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[TT_EXTINT | 0x1] = "External Interrupt 1",
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[TT_EXTINT | 0x2] = "External Interrupt 2",
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[TT_EXTINT | 0x3] = "External Interrupt 3",
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[TT_EXTINT | 0x4] = "External Interrupt 4",
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[TT_EXTINT | 0x5] = "External Interrupt 5",
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[TT_EXTINT | 0x6] = "External Interrupt 6",
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[TT_EXTINT | 0x7] = "External Interrupt 7",
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[TT_EXTINT | 0x8] = "External Interrupt 8",
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[TT_EXTINT | 0x9] = "External Interrupt 9",
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[TT_EXTINT | 0xa] = "External Interrupt 10",
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[TT_EXTINT | 0xb] = "External Interrupt 11",
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[TT_EXTINT | 0xc] = "External Interrupt 12",
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[TT_EXTINT | 0xd] = "External Interrupt 13",
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[TT_EXTINT | 0xe] = "External Interrupt 14",
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[TT_EXTINT | 0xf] = "External Interrupt 15",
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[TT_TOVF] = "Tag Overflow",
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[TT_CODE_ACCESS] = "Instruction Access Error",
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[TT_DATA_ACCESS] = "Data Access Error",
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[TT_DIV_ZERO] = "Division By Zero",
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[TT_NCP_INSN] = "Coprocessor Disabled",
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};
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#endif
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void do_interrupt(CPUState *env)
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{
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int cwp, intno = env->exception_index;
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#ifdef DEBUG_PCALL
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if (loglevel & CPU_LOG_INT) {
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static int count;
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const char *name;
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if (intno < 0 || intno >= 0x100)
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name = "Unknown";
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else if (intno >= 0x80)
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name = "Trap Instruction";
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else {
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name = excp_names[intno];
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if (!name)
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name = "Unknown";
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}
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fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
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count, name, intno,
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env->pc,
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env->npc, env->regwptr[6]);
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cpu_dump_state(env, logfile, fprintf, 0);
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#if 0
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{
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int i;
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uint8_t *ptr;
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fprintf(logfile, " code=");
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ptr = (uint8_t *)env->pc;
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for(i = 0; i < 16; i++) {
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fprintf(logfile, " %02x", ldub(ptr + i));
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}
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fprintf(logfile, "\n");
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}
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#endif
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count++;
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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if (env->psret == 0) {
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cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
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env->exception_index);
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return;
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}
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#endif
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env->psret = 0;
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cwp = (env->cwp - 1) & (NWINDOWS - 1);
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cpu_set_cwp(env, cwp);
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env->regwptr[9] = env->pc;
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env->regwptr[10] = env->npc;
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env->psrps = env->psrs;
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env->psrs = 1;
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env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
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env->pc = env->tbr;
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env->npc = env->pc + 4;
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env->exception_index = 0;
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}
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#endif
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void memcpy32(target_ulong *dst, const target_ulong *src)
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{
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dst[0] = src[0];
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@ -663,12 +878,6 @@ void memcpy32(target_ulong *dst, const target_ulong *src)
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dst[7] = src[7];
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}
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void helper_flush(target_ulong addr)
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{
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addr &= ~7;
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tb_invalidate_page_range(addr, addr + 8);
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}
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void cpu_reset(CPUSPARCState *env)
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{
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tlb_flush(env, 1);
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