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target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

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manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-02-13 07:54:04 -08:00
parent 7a50d3e2ae
commit f2ab172867
3 changed files with 34 additions and 30 deletions
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40
target/riscv/translate.c
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@ -198,12 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
CASE_OP_32_64(OPC_RISC_ADD):
tcg_gen_add_tl(source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_SUB):
tcg_gen_sub_tl(source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(source2, source2, 0x1F);
@ -220,9 +214,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
break;
case OPC_RISC_XOR:
tcg_gen_xor_tl(source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@ -248,12 +239,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(source1, source1, source2);
break;
case OPC_RISC_OR:
tcg_gen_or_tl(source1, source1, source2);
break;
case OPC_RISC_AND:
tcg_gen_and_tl(source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
@ -730,8 +715,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_add_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_sub_tl(ret, arg1, arg2);
tcg_gen_ext32s_tl(ret, ret);
}
#endif
static bool trans_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
source2 = tcg_temp_new();
gen_get_gpr(source1, a->rs1);
gen_get_gpr(source2, a->rs2);
(*func)(source1, source1, source2);
gen_set_gpr(a->rd, source1);
tcg_temp_free(source1);
tcg_temp_free(source2);
return true;
}
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"