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aspeed/smc: Add AST2600 timings registers

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Each CS has its own Read Timing Compensation Register on newer SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-13-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2019-11-19 15:12:06 +01:00 • committed by Peter Maydell
parent 2175eacfcd
commit f286f04c21
2 changed files with 15 additions and 3 deletions
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include/hw/ssi/aspeed_smc.h
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@ -40,6 +40,7 @@ typedef struct AspeedSMCController {
uint8_t r_ce_ctrl;
uint8_t r_ctrl0;
uint8_t r_timings;
uint8_t nregs_timings;
uint8_t conf_enable_w0;
uint8_t max_slaves;
const AspeedSegments *segments;