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target-m68k: Implement bitfield ops for memory

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Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-6-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Richard Henderson 2016-11-09 14:46:11 +01:00 • committed by Laurent Vivier
parent ac815f46a3
commit f2224f2c9a
4 changed files with 333 additions and 2 deletions
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142
target/m68k/translate.c
View file

@ -711,10 +711,17 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
case 0: /* Data register direct. */
case 1: /* Address register direct. */
return NULL_QREG;
case 2: /* Indirect register */
case 3: /* Indirect postincrement. */
if (opsize == OS_UNSIZED) {
return NULL_QREG;
}
/* fallthru */
case 2: /* Indirect register */
return get_areg(s, reg0);
case 4: /* Indirect predecrememnt. */
if (opsize == OS_UNSIZED) {
return NULL_QREG;
}
reg = get_areg(s, reg0);
tmp = tcg_temp_new();
tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
@ -3569,6 +3576,49 @@ DISAS_INSN(bfext_reg)
set_cc_op(s, CC_OP_LOGIC);
}
DISAS_INSN(bfext_mem)
{
int ext = read_im16(env, s);
int is_sign = insn & 0x200;
TCGv dest = DREG(ext, 12);
TCGv addr, len, ofs;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(extract32(ext, 6, 5));
}
if (is_sign) {
gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
tcg_gen_mov_i32(QREG_CC_N, dest);
} else {
TCGv_i64 tmp = tcg_temp_new_i64();
gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
tcg_temp_free_i64(tmp);
}
set_cc_op(s, CC_OP_LOGIC);
if (!(ext & 0x20)) {
tcg_temp_free(len);
}
if (!(ext & 0x800)) {
tcg_temp_free(ofs);
}
}
DISAS_INSN(bfop_reg)
{
int ext = read_im16(env, s);
@ -3634,6 +3684,54 @@ DISAS_INSN(bfop_reg)
tcg_temp_free(mask);
}
DISAS_INSN(bfop_mem)
{
int ext = read_im16(env, s);
TCGv addr, len, ofs;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(extract32(ext, 6, 5));
}
switch (insn & 0x0f00) {
case 0x0a00: /* bfchg */
gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
break;
case 0x0c00: /* bfclr */
gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
break;
case 0x0e00: /* bfset */
gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
break;
case 0x0800: /* bftst */
gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
break;
default:
g_assert_not_reached();
}
set_cc_op(s, CC_OP_LOGIC);
if (!(ext & 0x20)) {
tcg_temp_free(len);
}
if (!(ext & 0x800)) {
tcg_temp_free(ofs);
}
}
DISAS_INSN(bfins_reg)
{
int ext = read_im16(env, s);
@ -3708,6 +3806,40 @@ DISAS_INSN(bfins_reg)
tcg_temp_free(tmp);
}
DISAS_INSN(bfins_mem)
{
int ext = read_im16(env, s);
TCGv src = DREG(ext, 12);
TCGv addr, len, ofs;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
gen_addr_fault(s);
return;
}
if (ext & 0x20) {
len = DREG(ext, 0);
} else {
len = tcg_const_i32(extract32(ext, 0, 5));
}
if (ext & 0x800) {
ofs = DREG(ext, 6);
} else {
ofs = tcg_const_i32(extract32(ext, 6, 5));
}
gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
set_cc_op(s, CC_OP_LOGIC);
if (!(ext & 0x20)) {
tcg_temp_free(len);
}
if (!(ext & 0x800)) {
tcg_temp_free(ofs);
}
}
DISAS_INSN(ff1)
{
TCGv reg;
@ -4799,11 +4931,17 @@ void register_m68k_insns (CPUM68KState *env)
INSN(rotate8_reg, e030, f0f0, M68000);
INSN(rotate16_reg, e070, f0f0, M68000);
INSN(rotate_mem, e4c0, fcc0, M68000);
INSN(bfext_reg, e9c0, fdf8, BITFIELD); /* bfextu & bfexts */
INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
INSN(bfext_reg, e9c0, fdf8, BITFIELD);
INSN(bfins_mem, efc0, ffc0, BITFIELD);
INSN(bfins_reg, efc0, fff8, BITFIELD);
INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
INSN(undef_fpu, f000, f000, CF_ISA_A);
INSN(fpu, f200, ffc0, CF_FPU);