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target/loongarch: Implement LSX logic instructions
This patch includes: - V{AND/OR/XOR/NOR/ANDN/ORN}.V; - V{AND/OR/XOR/NOR}I.B. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-22-gaosong@loongson.cn>
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5 changed files with 94 additions and 0 deletions
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@ -2874,3 +2874,59 @@ TRANS(vmskltz_w, gen_vv, gen_helper_vmskltz_w)
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TRANS(vmskltz_d, gen_vv, gen_helper_vmskltz_d)
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TRANS(vmskgez_b, gen_vv, gen_helper_vmskgez_b)
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TRANS(vmsknz_b, gen_vv, gen_helper_vmsknz_b)
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TRANS(vand_v, gvec_vvv, MO_64, tcg_gen_gvec_and)
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TRANS(vor_v, gvec_vvv, MO_64, tcg_gen_gvec_or)
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TRANS(vxor_v, gvec_vvv, MO_64, tcg_gen_gvec_xor)
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TRANS(vnor_v, gvec_vvv, MO_64, tcg_gen_gvec_nor)
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static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
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{
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uint32_t vd_ofs, vj_ofs, vk_ofs;
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CHECK_SXE;
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vd_ofs = vec_full_offset(a->vd);
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vj_ofs = vec_full_offset(a->vj);
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vk_ofs = vec_full_offset(a->vk);
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tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, 16, ctx->vl/8);
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return true;
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}
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TRANS(vorn_v, gvec_vvv, MO_64, tcg_gen_gvec_orc)
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TRANS(vandi_b, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
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TRANS(vori_b, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
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TRANS(vxori_b, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
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static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
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{
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TCGv_vec t1;
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t1 = tcg_constant_vec_matching(t, vece, imm);
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tcg_gen_nor_vec(vece, t, a, t1);
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}
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static void gen_vnori_b(TCGv_i64 t, TCGv_i64 a, int64_t imm)
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{
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tcg_gen_movi_i64(t, dup_const(MO_8, imm));
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tcg_gen_nor_i64(t, a, t);
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}
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static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
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int64_t imm, uint32_t oprsz, uint32_t maxsz)
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{
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static const TCGOpcode vecop_list[] = {
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INDEX_op_nor_vec, 0
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};
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static const GVecGen2i op = {
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.fni8 = gen_vnori_b,
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.fniv = gen_vnori,
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.fnoi = gen_helper_vnori_b,
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.opt_opc = vecop_list,
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.vece = MO_8
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};
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tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op);
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}
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TRANS(vnori_b, gvec_vv_i, MO_8, do_vnori_b)
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