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target/avr: Introduce basic CPU class object

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This patch introduces AVR CPU class object and its basic elements
and functions.

[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[thuth: Adjusted reset and parent_reset handling]
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-3-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik 2020-01-26 19:51:34 +01:00 • committed by Philippe Mathieu-Daudé
parent c8c0d267fd
commit f1c671f96c
3 changed files with 399 additions and 0 deletions
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139
target/avr/cpu.h
View file

@ -21,8 +21,17 @@
#ifndef QEMU_AVR_CPU_H
#define QEMU_AVR_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
#endif
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
#define TCG_GUEST_DEFAULT_MO 0
/*
@ -63,4 +72,134 @@
*/
#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
typedef struct CPUAVRState CPUAVRState;
struct CPUAVRState {
uint32_t pc_w; /* 0x003fffff up to 22 bits */
uint32_t sregC; /* 0x00000001 1 bit */
uint32_t sregZ; /* 0x00000001 1 bit */
uint32_t sregN; /* 0x00000001 1 bit */
uint32_t sregV; /* 0x00000001 1 bit */
uint32_t sregS; /* 0x00000001 1 bit */
uint32_t sregH; /* 0x00000001 1 bit */
uint32_t sregT; /* 0x00000001 1 bit */
uint32_t sregI; /* 0x00000001 1 bit */
uint32_t rampD; /* 0x00ff0000 8 bits */
uint32_t rampX; /* 0x00ff0000 8 bits */
uint32_t rampY; /* 0x00ff0000 8 bits */
uint32_t rampZ; /* 0x00ff0000 8 bits */
uint32_t eind; /* 0x00ff0000 8 bits */
uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */
uint32_t sp; /* 16 bits */
uint32_t skip; /* if set skip instruction */
uint64_t intsrc; /* interrupt sources */
bool fullacc; /* CPU/MEM if true MEM only otherwise */
uint64_t features;
};
/**
* AVRCPU:
* @env: #CPUAVRState
*
* A AVR CPU.
*/
typedef struct AVRCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAVRState env;
} AVRCPU;
void avr_cpu_do_interrupt(CPUState *cpu);
bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#define cpu_list avr_cpu_list
#define cpu_signal_handler cpu_avr_signal_handler
#define cpu_mmu_index avr_cpu_mmu_index
static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
{
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
}
void avr_cpu_tcg_init(void);
void avr_cpu_list(void);
int cpu_avr_exec(CPUState *cpu);
int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,
int len, bool is_write);
enum {
TB_FLAGS_FULL_ACCESS = 1,
TB_FLAGS_SKIP = 2,
};
static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags = 0;
*pc = env->pc_w * 2;
*cs_base = 0;
if (env->fullacc) {
flags |= TB_FLAGS_FULL_ACCESS;
}
if (env->skip) {
flags |= TB_FLAGS_SKIP;
}
*pflags = flags;
}
static inline int cpu_interrupts_enabled(CPUAVRState *env)
{
return env->sregI != 0;
}
static inline uint8_t cpu_get_sreg(CPUAVRState *env)
{
uint8_t sreg;
sreg = (env->sregC) << 0
| (env->sregZ) << 1
| (env->sregN) << 2
| (env->sregV) << 3
| (env->sregS) << 4
| (env->sregH) << 5
| (env->sregT) << 6
| (env->sregI) << 7;
return sreg;
}
static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
{
env->sregC = (sreg >> 0) & 0x01;
env->sregZ = (sreg >> 1) & 0x01;
env->sregN = (sreg >> 2) & 0x01;
env->sregV = (sreg >> 3) & 0x01;
env->sregS = (sreg >> 4) & 0x01;
env->sregH = (sreg >> 5) & 0x01;
env->sregT = (sreg >> 6) & 0x01;
env->sregI = (sreg >> 7) & 0x01;
}
bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
typedef CPUAVRState CPUArchState;
typedef AVRCPU ArchCPU;
#include "exec/cpu-all.h"
#endif /* !defined (QEMU_AVR_CPU_H) */