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hw/pci: spelling fixes

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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Michael Tokarev 2023-07-14 14:27:04 +03:00
parent 2431f4f184
commit f1c0cff8a2
13 changed files with 17 additions and 17 deletions
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4
hw/pci-host/gt64120.c
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@ -331,9 +331,9 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
/*
* The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
* Command Register determines how data transactions from the CPU to/from
* PCI are handled along with the setting of the Endianess bit in the CPU
* PCI are handled along with the setting of the Endianness bit in the CPU
* Configuration Register. See:
* - Table 16: 32-bit PCI Transaction Endianess
* - Table 16: 32-bit PCI Transaction Endianness
* - Table 158: PCI_0 Command, Offset: 0xc00
*/