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q800: reimplement mac-io region aliasing using IO memory region
The current use of aliased memory regions causes us 2 problems: firstly the output of "info qom-tree" is absolutely huge and difficult to read, and secondly we have already reached the internal limit for memory regions as adding any new memory region into the mac-io region causes QEMU to assert with "phys_section_add: Assertion `map->sections_nb < TARGET_PAGE_SIZE' failed". Implement the mac-io region aliasing using a single IO memory region that applies IO_SLICE_MASK representing the maximum size of the aliased region and then forwarding the access to the existing mac-io memory region using the address space API. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
parent
7527c52fd0
commit
f18a288632
2 changed files with 82 additions and 19 deletions
100
hw/m68k/q800.c
100
hw/m68k/q800.c
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@ -59,6 +59,7 @@
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#define IO_BASE 0x50000000
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#define IO_BASE 0x50000000
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#define IO_SLICE 0x00040000
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#define IO_SLICE 0x00040000
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#define IO_SLICE_MASK (IO_SLICE - 1)
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#define IO_SIZE 0x04000000
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#define IO_SIZE 0x04000000
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#define VIA_BASE (IO_BASE + 0x00000)
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#define VIA_BASE (IO_BASE + 0x00000)
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@ -127,6 +128,68 @@ static uint8_t fake_mac_rom[] = {
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0x60, 0xFE /* bras [self] */
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0x60, 0xFE /* bras [self] */
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};
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};
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static MemTxResult macio_alias_read(void *opaque, hwaddr addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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MemTxResult r;
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uint32_t val;
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addr &= IO_SLICE_MASK;
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addr |= IO_BASE;
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switch (size) {
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case 4:
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val = address_space_ldl_be(&address_space_memory, addr, attrs, &r);
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break;
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case 2:
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val = address_space_lduw_be(&address_space_memory, addr, attrs, &r);
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break;
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case 1:
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val = address_space_ldub(&address_space_memory, addr, attrs, &r);
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break;
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default:
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g_assert_not_reached();
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}
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*data = val;
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return r;
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}
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static MemTxResult macio_alias_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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MemTxResult r;
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addr &= IO_SLICE_MASK;
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addr |= IO_BASE;
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switch (size) {
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case 4:
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address_space_stl_be(&address_space_memory, addr, value, attrs, &r);
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break;
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case 2:
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address_space_stw_be(&address_space_memory, addr, value, attrs, &r);
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break;
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case 1:
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address_space_stb(&address_space_memory, addr, value, attrs, &r);
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break;
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default:
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g_assert_not_reached();
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}
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return r;
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}
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static const MemoryRegionOps macio_alias_ops = {
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.read_with_attrs = macio_alias_read,
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.write_with_attrs = macio_alias_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void q800_machine_init(MachineState *machine)
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static void q800_machine_init(MachineState *machine)
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{
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{
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Q800MachineState *m = Q800_MACHINE(machine);
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Q800MachineState *m = Q800_MACHINE(machine);
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@ -137,10 +200,8 @@ static void q800_machine_init(MachineState *machine)
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int bios_size;
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int bios_size;
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ram_addr_t initrd_base;
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ram_addr_t initrd_base;
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int32_t initrd_size;
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int32_t initrd_size;
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MemoryRegion *io;
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MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
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MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
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uint8_t *prom;
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uint8_t *prom;
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const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1;
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int i, checksum;
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int i, checksum;
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MacFbMode *macfb_mode;
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MacFbMode *macfb_mode;
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ram_addr_t ram_size = machine->ram_size;
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ram_addr_t ram_size = machine->ram_size;
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@ -187,16 +248,10 @@ static void q800_machine_init(MachineState *machine)
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* Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
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* Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
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* from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
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* from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
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*/
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*/
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io = g_new(MemoryRegion, io_slice_nb);
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memory_region_init_io(&m->macio_alias, OBJECT(machine), &macio_alias_ops,
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for (i = 0; i < io_slice_nb; i++) {
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&m->macio, "mac-io.alias", IO_SIZE - IO_SLICE);
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char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1);
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memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE,
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&m->macio_alias);
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memory_region_init_alias(&io[i], NULL, name, get_system_memory(),
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IO_BASE, IO_SLICE);
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memory_region_add_subregion(get_system_memory(),
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IO_BASE + (i + 1) * IO_SLICE, &io[i]);
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g_free(name);
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}
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/* IRQ Glue */
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/* IRQ Glue */
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object_initialize_child(OBJECT(machine), "glue", &m->glue, TYPE_GLUE);
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object_initialize_child(OBJECT(machine), "glue", &m->glue, TYPE_GLUE);
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@ -212,7 +267,8 @@ static void q800_machine_init(MachineState *machine)
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}
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}
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sysbus = SYS_BUS_DEVICE(via1_dev);
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sysbus = SYS_BUS_DEVICE(via1_dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 1, VIA_BASE);
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memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE,
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sysbus_mmio_get_region(sysbus, 1));
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sysbus_connect_irq(sysbus, 0,
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sysbus_connect_irq(sysbus, 0,
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qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA1));
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qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA1));
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/* A/UX mode */
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/* A/UX mode */
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@ -230,7 +286,8 @@ static void q800_machine_init(MachineState *machine)
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via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2);
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via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2);
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sysbus = SYS_BUS_DEVICE(via2_dev);
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sysbus = SYS_BUS_DEVICE(via2_dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
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memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE + VIA_SIZE,
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sysbus_mmio_get_region(sysbus, 1));
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sysbus_connect_irq(sysbus, 0,
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sysbus_connect_irq(sysbus, 0,
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qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA2));
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qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA2));
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@ -264,7 +321,8 @@ static void q800_machine_init(MachineState *machine)
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OBJECT(get_system_memory()), &error_abort);
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OBJECT(get_system_memory()), &error_abort);
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 0, SONIC_BASE);
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memory_region_add_subregion(&m->macio, SONIC_BASE - IO_BASE,
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sysbus_mmio_get_region(sysbus, 0));
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sysbus_connect_irq(sysbus, 0,
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sysbus_connect_irq(sysbus, 0,
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qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_SONIC));
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qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_SONIC));
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@ -305,7 +363,8 @@ static void q800_machine_init(MachineState *machine)
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qdev_connect_gpio_out(escc_orgate, 0,
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qdev_connect_gpio_out(escc_orgate, 0,
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qdev_get_gpio_in(DEVICE(&m->glue),
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qdev_get_gpio_in(DEVICE(&m->glue),
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GLUE_IRQ_IN_ESCC));
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GLUE_IRQ_IN_ESCC));
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sysbus_mmio_map(sysbus, 0, SCC_BASE);
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memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE,
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sysbus_mmio_get_region(sysbus, 0));
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/* SCSI */
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/* SCSI */
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VIA2_IRQ_SCSI_BIT)));
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VIA2_IRQ_SCSI_BIT)));
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sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
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sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
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VIA2_IRQ_SCSI_DATA_BIT)));
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VIA2_IRQ_SCSI_DATA_BIT)));
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sysbus_mmio_map(sysbus, 0, ESP_BASE);
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memory_region_add_subregion(&m->macio, ESP_BASE - IO_BASE,
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sysbus_mmio_map(sysbus, 1, ESP_PDMA);
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sysbus_mmio_get_region(sysbus, 0));
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memory_region_add_subregion(&m->macio, ESP_PDMA - IO_BASE,
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sysbus_mmio_get_region(sysbus, 1));
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scsi_bus_legacy_handle_cmdline(&esp->bus);
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scsi_bus_legacy_handle_cmdline(&esp->bus);
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@ -334,7 +395,8 @@ static void q800_machine_init(MachineState *machine)
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dev = qdev_new(TYPE_SWIM);
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dev = qdev_new(TYPE_SWIM);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
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memory_region_add_subregion(&m->macio, SWIM_BASE - IO_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
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/* NuBus */
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/* NuBus */
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@ -40,6 +40,7 @@ struct Q800MachineState {
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MemoryRegion rom;
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MemoryRegion rom;
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GLUEState glue;
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GLUEState glue;
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MemoryRegion macio;
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MemoryRegion macio;
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MemoryRegion macio_alias;
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};
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};
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#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
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#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
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