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RISC-V: Add misa runtime write support

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This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Michael Clark 2019-01-14 23:59:00 +00:00 • committed by Palmer Dabbelt
parent d77c3401e6
commit f18637cd61
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4 changed files with 68 additions and 3 deletions
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target/riscv/cpu.c
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@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo {
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa = misa;
env->misa_mask = env->misa = misa;
}
static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)