motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/mips: Add missing default cases for some nanoMIPS pools

Browse source 
Switch statements for the code segments that handle nanoMIPS
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.

Fix this by adding default cases for these switch statements that
trigger reserved instruction exception.

Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-7-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Stefan Pejic 2022-05-04 13:04:02 +02:00 • committed by Philippe Mathieu-Daudé
parent db7596989a
commit f1663114df
1 changed files with 19 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

19
target/mips/tcg/nanomips_translate.c.inc
View file

@ -2707,6 +2707,9 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_SDC1XS:
tcg_gen_shli_tl(t0, t0, 3);
break;
default:
gen_reserved_instruction(ctx);
goto out;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
@ -2797,6 +2800,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
break;
}
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@ -3944,6 +3948,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_shift_imm(ctx, OPC_ROTR, rt, rs,
extract32(ctx->opcode, 0, 5));
break;
default:
gen_reserved_instruction(ctx);
break;
}
}
break;
@ -4245,6 +4252,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_SC:
@ -4257,6 +4267,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
false);
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_CACHE:
@ -4265,6 +4278,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_cache_operation(ctx, rt, rs, s);
}
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_LS_E0:
@ -4371,6 +4387,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
default:
gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_LS_WM: