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target/riscv: Pass ra to riscv_csrrw

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250425152311.804338-5-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2025-04-25 08:23:08 -07:00 • committed by Alistair Francis
parent c26c4afd0f
commit f1304836ea
4 changed files with 11 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/riscv/riscv_hart.c
View file

@ -72,7 +72,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
ret = riscv_csrr(env, csrno, (target_ulong *)val); ret = riscv_csrr(env, csrno, (target_ulong *)val);
} else if (strcmp(cmd, "set_csr") == 0) { } else if (strcmp(cmd, "set_csr") == 0) {
ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
} }
g_assert(ret == RISCV_EXCP_NONE); g_assert(ret == RISCV_EXCP_NONE);

8
target/riscv/cpu.h
View file

@ -813,8 +813,8 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno,
target_ulong *ret_value); target_ulong *ret_value);
RISCVException riscv_csrrw(CPURISCVState *env, int csrno, RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong *ret_value, target_ulong new_value,
target_ulong new_value, target_ulong write_mask); target_ulong write_mask, uintptr_t ra);
RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong *ret_value,
target_ulong new_value, target_ulong new_value,
@ -823,13 +823,13 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
static inline void riscv_csr_write(CPURISCVState *env, int csrno, static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
} }
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{ {
target_ulong val = 0; target_ulong val = 0;
riscv_csrrw(env, csrno, &val, 0, 0); riscv_csrrw(env, csrno, &val, 0, 0, 0);
return val; return val;
} }

8
target/riscv/csr.c
View file

@ -5574,15 +5574,15 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno,
} }
RISCVException riscv_csrrw(CPURISCVState *env, int csrno, RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong *ret_value, target_ulong new_value,
target_ulong new_value, target_ulong write_mask) target_ulong write_mask, uintptr_t ra)
{ {
RISCVException ret = riscv_csrrw_check(env, csrno, true); RISCVException ret = riscv_csrrw_check(env, csrno, true);
if (ret != RISCV_EXCP_NONE) { if (ret != RISCV_EXCP_NONE) {
return ret; return ret;
} }
return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, 0); return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, ra);
} }
static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
@ -5704,7 +5704,7 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
if (!write_mask) { if (!write_mask) {
ret = riscv_csrr(env, csrno, ret_value); ret = riscv_csrr(env, csrno, ret_value);
} else { } else {
ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask, 0);
} }
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
env->debugger = false; env->debugger = false;

4
target/riscv/op_helper.c
View file

@ -71,7 +71,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
void helper_csrw(CPURISCVState *env, int csr, target_ulong src) void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
{ {
target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask); RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask, GETPC());
if (ret != RISCV_EXCP_NONE) { if (ret != RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC()); riscv_raise_exception(env, ret, GETPC());
@ -82,7 +82,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
target_ulong src, target_ulong write_mask) target_ulong src, target_ulong write_mask)
{ {
target_ulong val = 0; target_ulong val = 0;
RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask); RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask, GETPC());
if (ret != RISCV_EXCP_NONE) { if (ret != RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC()); riscv_raise_exception(env, ret, GETPC());