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pci-bridge: Turn PCIBridge into abstract QOM type

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Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts.

Reviewed-by: Don Koch <dkoch@verizon.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
[AF: Updated pbm-bridge parent to TYPE_PCI_BRIDGE]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-07-11 17:13:43 +02:00
parent 45c0a675f9
commit f055e96bd4
11 changed files with 78 additions and 55 deletions
Download patch file Download diff file Expand all files Collapse all files

18
hw/pci-bridge/xio3130_downstream.c
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@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)
static int xio3130_downstream_initfn(PCIDevice *d)
{
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc;
@ -113,7 +113,7 @@ err_bridge:
static void xio3130_downstream_exitfn(PCIDevice *d)
{
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
PCIBridge *br = PCI_BRIDGE(d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
if (!d) {
return NULL;
}
br = DO_UPCAST(PCIBridge, dev, d);
br = PCI_BRIDGE(d);
qdev = &br->dev.qdev;
qdev = DEVICE(d);
pci_bridge_map_irq(br, bus_name, map_irq);
qdev_prop_set_uint8(qdev, "port", port);
qdev_prop_set_uint8(qdev, "chassis", chassis);
@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downstream = {
.minimum_version_id_old = 1,
.post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot),
VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0,
vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST()
}
@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] = {
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
port.br.dev.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT),
port.br.parent_obj.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(),
};
@ -196,7 +196,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
static const TypeInfo xio3130_downstream_info = {
.name = "xio3130-downstream",
.parent = TYPE_PCI_DEVICE,
.parent = TYPE_PCI_BRIDGE,
.instance_size = sizeof(PCIESlot),
.class_init = xio3130_downstream_class_init,
};