mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 01:03:55 -06:00
This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
- Allows 16-bit writes to the SiFive test device. This fixes the
failure to reboot the RISC-V virt machine
- Support for the Microchip PolarFire SoC and Icicle Kit
- A reafactor of RISC-V code out of hw/riscv
-----BEGIN PGP SIGNATURE-----
iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAl9aa4YACgkQIeENKd+X
cFTJjgf5ASfFIO5HqP1l80/UM5Pswyq0IROZDq0ItZa6U4EPzLXoE2N0POriIj4h
Ds2JbMg0ORDqY0VbSxHlgYHMgJ9S6cuVOMnATsPG0d2jaJ3gSxLBu5k/1ENqe+Vw
sSYXZv5uEAUfOFz99zbuhKHct5HzlmBFW9dVHdflUQS+cRgsSXq27mz1BvZ8xMWl
lMhwubqdoNx0rOD3vKnlwrxaf54DcJ2IQT3BtTCjEar3tukdNaLijAuwt2hrFyr+
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=07oA
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging
This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
- Allows 16-bit writes to the SiFive test device. This fixes the
failure to reboot the RISC-V virt machine
- Support for the Microchip PolarFire SoC and Icicle Kit
- A reafactor of RISC-V code out of hw/riscv
# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
hw/riscv: Sort the Kconfig options in alphabetical order
hw/riscv: Drop CONFIG_SIFIVE
hw/riscv: Always build riscv_hart.c
hw/riscv: Move sifive_test model to hw/misc
hw/riscv: Move sifive_uart model to hw/char
hw/riscv: Move riscv_htif model to hw/char
hw/riscv: Move sifive_plic model to hw/intc
hw/riscv: Move sifive_clint model to hw/intc
hw/riscv: Move sifive_gpio model to hw/gpio
hw/riscv: Move sifive_u_otp model to hw/misc
hw/riscv: Move sifive_u_prci model to hw/misc
hw/riscv: Move sifive_e_prci model to hw/misc
hw/riscv: sifive_u: Connect a DMA controller
hw/riscv: clint: Avoid using hard-coded timebase frequency
hw/riscv: microchip_pfsoc: Hook GPIO controllers
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
hw/net: cadence_gem: Add a new 'phy-addr' property
hw/riscv: microchip_pfsoc: Connect a DMA controller
hw/dma: Add SiFive platform DMA controller emulation
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# hw/riscv/trace-events
This commit is contained in:
Peter Maydell
commit
f00f57f344
64 changed files with 1577 additions and 107 deletions
|
|
@ -7,3 +7,6 @@ config PL061
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|||
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config GPIO_KEY
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bool
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config SIFIVE_GPIO
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bool
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|
|
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|||
|
|
@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
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softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
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softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
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softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
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softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
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397
hw/gpio/sifive_gpio.c
Normal file
397
hw/gpio/sifive_gpio.c
Normal file
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@ -0,0 +1,397 @@
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/*
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* SiFive System-on-Chip general purpose input/output register definition
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*
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* Copyright 2019 AdaCore
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*
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* Base on nrf51_gpio.c:
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*
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* Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/gpio/sifive_gpio.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static void update_output_irq(SIFIVEGPIOState *s)
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{
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uint32_t pending;
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uint32_t pin;
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pending = s->high_ip & s->high_ie;
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pending |= s->low_ip & s->low_ie;
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pending |= s->rise_ip & s->rise_ie;
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pending |= s->fall_ip & s->fall_ie;
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for (int i = 0; i < s->ngpio; i++) {
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pin = 1 << i;
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qemu_set_irq(s->irq[i], (pending & pin) != 0);
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trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
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}
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}
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static void update_state(SIFIVEGPIOState *s)
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{
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size_t i;
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bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
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rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
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for (i = 0; i < s->ngpio; i++) {
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prev_ival = extract32(s->value, i, 1);
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in = extract32(s->in, i, 1);
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in_mask = extract32(s->in_mask, i, 1);
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port = extract32(s->port, i, 1);
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out_xor = extract32(s->out_xor, i, 1);
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pull = extract32(s->pue, i, 1);
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output_en = extract32(s->output_en, i, 1);
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input_en = extract32(s->input_en, i, 1);
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rise_ip = extract32(s->rise_ip, i, 1);
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fall_ip = extract32(s->fall_ip, i, 1);
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low_ip = extract32(s->low_ip, i, 1);
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high_ip = extract32(s->high_ip, i, 1);
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/* Output value (IOF not supported) */
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oval = output_en && (port ^ out_xor);
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/* Pin both driven externally and internally */
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if (output_en && in_mask) {
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qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i);
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}
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if (in_mask) {
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/* The pin is driven by external device */
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actual_value = in;
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} else if (output_en) {
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/* The pin is driven by internal circuit */
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actual_value = oval;
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} else {
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/* Floating? Apply pull-up resistor */
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actual_value = pull;
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}
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if (output_en) {
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qemu_set_irq(s->output[i], actual_value);
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}
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/* Input value */
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ival = input_en && actual_value;
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/* Interrupts */
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high_ip = high_ip || ival;
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s->high_ip = deposit32(s->high_ip, i, 1, high_ip);
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low_ip = low_ip || !ival;
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s->low_ip = deposit32(s->low_ip, i, 1, low_ip);
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rise_ip = rise_ip || (ival && !prev_ival);
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s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip);
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fall_ip = fall_ip || (!ival && prev_ival);
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s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip);
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/* Update value */
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s->value = deposit32(s->value, i, 1, ival);
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}
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update_output_irq(s);
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}
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static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
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{
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SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
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uint64_t r = 0;
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switch (offset) {
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case SIFIVE_GPIO_REG_VALUE:
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r = s->value;
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break;
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case SIFIVE_GPIO_REG_INPUT_EN:
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r = s->input_en;
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break;
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case SIFIVE_GPIO_REG_OUTPUT_EN:
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r = s->output_en;
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break;
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case SIFIVE_GPIO_REG_PORT:
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r = s->port;
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break;
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case SIFIVE_GPIO_REG_PUE:
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r = s->pue;
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break;
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case SIFIVE_GPIO_REG_DS:
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r = s->ds;
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break;
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case SIFIVE_GPIO_REG_RISE_IE:
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r = s->rise_ie;
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break;
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case SIFIVE_GPIO_REG_RISE_IP:
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r = s->rise_ip;
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break;
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case SIFIVE_GPIO_REG_FALL_IE:
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r = s->fall_ie;
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break;
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case SIFIVE_GPIO_REG_FALL_IP:
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r = s->fall_ip;
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break;
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case SIFIVE_GPIO_REG_HIGH_IE:
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r = s->high_ie;
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break;
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case SIFIVE_GPIO_REG_HIGH_IP:
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r = s->high_ip;
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break;
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case SIFIVE_GPIO_REG_LOW_IE:
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r = s->low_ie;
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break;
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case SIFIVE_GPIO_REG_LOW_IP:
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r = s->low_ip;
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break;
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case SIFIVE_GPIO_REG_IOF_EN:
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r = s->iof_en;
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break;
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case SIFIVE_GPIO_REG_IOF_SEL:
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r = s->iof_sel;
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break;
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case SIFIVE_GPIO_REG_OUT_XOR:
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r = s->out_xor;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: bad read offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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trace_sifive_gpio_read(offset, r);
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return r;
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}
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static void sifive_gpio_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned int size)
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{
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SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
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trace_sifive_gpio_write(offset, value);
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switch (offset) {
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case SIFIVE_GPIO_REG_INPUT_EN:
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s->input_en = value;
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break;
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case SIFIVE_GPIO_REG_OUTPUT_EN:
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s->output_en = value;
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break;
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case SIFIVE_GPIO_REG_PORT:
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s->port = value;
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break;
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case SIFIVE_GPIO_REG_PUE:
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s->pue = value;
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break;
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case SIFIVE_GPIO_REG_DS:
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s->ds = value;
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break;
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case SIFIVE_GPIO_REG_RISE_IE:
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s->rise_ie = value;
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break;
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case SIFIVE_GPIO_REG_RISE_IP:
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/* Write 1 to clear */
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s->rise_ip &= ~value;
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break;
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case SIFIVE_GPIO_REG_FALL_IE:
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s->fall_ie = value;
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break;
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case SIFIVE_GPIO_REG_FALL_IP:
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/* Write 1 to clear */
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s->fall_ip &= ~value;
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break;
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case SIFIVE_GPIO_REG_HIGH_IE:
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s->high_ie = value;
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break;
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case SIFIVE_GPIO_REG_HIGH_IP:
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/* Write 1 to clear */
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s->high_ip &= ~value;
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break;
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case SIFIVE_GPIO_REG_LOW_IE:
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s->low_ie = value;
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break;
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case SIFIVE_GPIO_REG_LOW_IP:
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/* Write 1 to clear */
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s->low_ip &= ~value;
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break;
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case SIFIVE_GPIO_REG_IOF_EN:
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s->iof_en = value;
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break;
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case SIFIVE_GPIO_REG_IOF_SEL:
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s->iof_sel = value;
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break;
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case SIFIVE_GPIO_REG_OUT_XOR:
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s->out_xor = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: bad write offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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update_state(s);
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}
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static const MemoryRegionOps gpio_ops = {
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.read = sifive_gpio_read,
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.write = sifive_gpio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static void sifive_gpio_set(void *opaque, int line, int value)
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{
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SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
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trace_sifive_gpio_set(line, value);
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assert(line >= 0 && line < SIFIVE_GPIO_PINS);
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s->in_mask = deposit32(s->in_mask, line, 1, value >= 0);
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if (value >= 0) {
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||||
s->in = deposit32(s->in, line, 1, value != 0);
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||||
}
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|
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update_state(s);
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}
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|
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static void sifive_gpio_reset(DeviceState *dev)
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||||
{
|
||||
SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
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||||
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||||
s->value = 0;
|
||||
s->input_en = 0;
|
||||
s->output_en = 0;
|
||||
s->port = 0;
|
||||
s->pue = 0;
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||||
s->ds = 0;
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||||
s->rise_ie = 0;
|
||||
s->rise_ip = 0;
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s->fall_ie = 0;
|
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s->fall_ip = 0;
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s->high_ie = 0;
|
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s->high_ip = 0;
|
||||
s->low_ie = 0;
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||||
s->low_ip = 0;
|
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s->iof_en = 0;
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s->iof_sel = 0;
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s->out_xor = 0;
|
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s->in = 0;
|
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s->in_mask = 0;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_sifive_gpio = {
|
||||
.name = TYPE_SIFIVE_GPIO,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(value, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(input_en, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(output_en, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(port, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(pue, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(rise_ie, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(rise_ip, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(fall_ie, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(fall_ip, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(high_ie, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(high_ip, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(low_ie, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(low_ip, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(in, SIFIVEGPIOState),
|
||||
VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static Property sifive_gpio_properties[] = {
|
||||
DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void sifive_gpio_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
|
||||
|
||||
memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s,
|
||||
TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
|
||||
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
|
||||
|
||||
for (int i = 0; i < s->ngpio; i++) {
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
|
||||
}
|
||||
|
||||
qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio);
|
||||
qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio);
|
||||
}
|
||||
|
||||
static void sifive_gpio_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
device_class_set_props(dc, sifive_gpio_properties);
|
||||
dc->vmsd = &vmstate_sifive_gpio;
|
||||
dc->realize = sifive_gpio_realize;
|
||||
dc->reset = sifive_gpio_reset;
|
||||
dc->desc = "SiFive GPIO";
|
||||
}
|
||||
|
||||
static const TypeInfo sifive_gpio_info = {
|
||||
.name = TYPE_SIFIVE_GPIO,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SIFIVEGPIOState),
|
||||
.class_init = sifive_gpio_class_init
|
||||
};
|
||||
|
||||
static void sifive_gpio_register_types(void)
|
||||
{
|
||||
type_register_static(&sifive_gpio_info);
|
||||
}
|
||||
|
||||
type_init(sifive_gpio_register_types)
|
||||
|
|
@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
|
|||
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
|
||||
nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
|
||||
nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
|
||||
|
||||
# sifive_gpio.c
|
||||
sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
|
||||
sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
|
||||
sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
|
||||
sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue