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target/arm: Annotate arm_max_initfn with FEAT identifiers
Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
b6f8b358c2
commit
ef696cfbae
2 changed files with 74 additions and 74 deletions
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@ -713,51 +713,51 @@ static void aarch64_max_initfn(Object *obj)
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cpu->midr = t;
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
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t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
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t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
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t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
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t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
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t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
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t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
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t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
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t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
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t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
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cpu->isar.id_aa64isar0 = t;
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
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t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
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t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
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t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
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t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
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t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
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t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
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t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
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t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
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t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
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cpu->isar.id_aa64pfr0 = t;
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
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t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
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t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
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/*
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* Begin with full support for MTE. This will be downgraded to MTE=0
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* during realize if the board provides no tag memory, much like
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* we do for EL2 with the virtualization=on property.
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*/
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t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
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t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
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cpu->isar.id_aa64pfr1 = t;
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t = cpu->isar.id_aa64mmfr0;
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@ -769,37 +769,37 @@ static void aarch64_max_initfn(Object *obj)
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cpu->isar.id_aa64mmfr0 = t;
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t = cpu->isar.id_aa64mmfr1;
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t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
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t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
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t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
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t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
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t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
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t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
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t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
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t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
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t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
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t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
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cpu->isar.id_aa64mmfr1 = t;
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t = cpu->isar.id_aa64mmfr2;
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t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
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t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
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t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
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t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
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t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
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t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
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t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
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t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
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t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
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t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
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t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
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t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
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cpu->isar.id_aa64mmfr2 = t;
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t = cpu->isar.id_aa64zfr0;
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t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
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t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
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t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
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t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
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t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
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t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
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t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
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cpu->isar.id_aa64zfr0 = t;
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t = cpu->isar.id_aa64dfr0;
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t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
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t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
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cpu->isar.id_aa64dfr0 = t;
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/* Replicate the same data to the 32-bit id registers. */
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