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hw/riscv: opentitan: Update to the latest build

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Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-10-18 12:38:39 +10:00
parent b550f89457
commit ef63100648
2 changed files with 20 additions and 8 deletions
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6
include/hw/riscv/opentitan.h
View file

@ -20,7 +20,7 @@
#define HW_OPENTITAN_H
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "qom/object.h"
@ -34,7 +34,7 @@ struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
IbexPlicState plic;
SiFivePLICState plic;
IbexUartState uart;
IbexTimerState timer;
@ -87,7 +87,7 @@ enum {
};
enum {
IBEX_TIMER_TIMEREXPIRED0_0 = 125,
IBEX_TIMER_TIMEREXPIRED0_0 = 126,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,