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target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*

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The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers.  So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
This commit is contained in:
Brian Cain 2024-08-26 17:26:30 -07:00 • committed by Brian Cain
parent 0cb73cb5a0
commit eed3f35879
5 changed files with 15 additions and 14 deletions
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4
linux-user/hexagon/cpu_loop.c
View file

@ -42,7 +42,7 @@ void cpu_loop(CPUHexagonState *env)
case EXCP_INTERRUPT: case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */ /* just indicate that signals should be handled asap */
break; break;
case HEX_EXCP_TRAP0: case HEX_EVENT_TRAP0:
syscallnum = env->gpr[6]; syscallnum = env->gpr[6];
env->gpr[HEX_REG_PC] += 4; env->gpr[HEX_REG_PC] += 4;
ret = do_syscall(env, ret = do_syscall(env,
@ -60,7 +60,7 @@ void cpu_loop(CPUHexagonState *env)
env->gpr[0] = ret; env->gpr[0] = ret;
} }
break; break;
case HEX_EXCP_PC_NOT_ALIGNED: case HEX_CAUSE_PC_NOT_ALIGNED:
force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
env->gpr[HEX_REG_R31]); env->gpr[HEX_REG_R31]);
break; break;

2
target/hexagon/cpu.h
View file

@ -143,7 +143,7 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
} }
*flags = hex_flags; *flags = hex_flags;
if (*pc & PCALIGN_MASK) { if (*pc & PCALIGN_MASK) {
hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0); hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
} }
} }

15
target/hexagon/cpu_bits.h
View file

@ -23,14 +23,15 @@
#define PCALIGN 4 #define PCALIGN 4
#define PCALIGN_MASK (PCALIGN - 1) #define PCALIGN_MASK (PCALIGN - 1)
#define HEX_EXCP_FETCH_NO_UPAGE 0x012 #define HEX_EVENT_TRAP0 0x008
#define HEX_EXCP_INVALID_PACKET 0x015
#define HEX_EXCP_INVALID_OPCODE 0x015
#define HEX_EXCP_PC_NOT_ALIGNED 0x01e
#define HEX_EXCP_PRIV_NO_UREAD 0x024
#define HEX_EXCP_PRIV_NO_UWRITE 0x025
#define HEX_EXCP_TRAP0 0x172 #define HEX_CAUSE_TRAP0 0x172
#define HEX_CAUSE_FETCH_NO_UPAGE 0x012
#define HEX_CAUSE_INVALID_PACKET 0x015
#define HEX_CAUSE_INVALID_OPCODE 0x015
#define HEX_CAUSE_PC_NOT_ALIGNED 0x01e
#define HEX_CAUSE_PRIV_NO_UREAD 0x024
#define HEX_CAUSE_PRIV_NO_UWRITE 0x025
#define PACKET_WORDS_MAX 4 #define PACKET_WORDS_MAX 4

2
target/hexagon/gen_tcg.h
View file

@ -1365,7 +1365,7 @@
do { \ do { \
uiV = uiV; \ uiV = uiV; \
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \ TCGv excp = tcg_constant_tl(HEX_EVENT_TRAP0); \
gen_helper_raise_exception(tcg_env, excp); \ gen_helper_raise_exception(tcg_env, excp); \
} while (0) } while (0)
#endif #endif

6
target/hexagon/translate.c
View file

@ -558,7 +558,7 @@ static void gen_insn(DisasContext *ctx)
ctx->insn->generate(ctx); ctx->insn->generate(ctx);
mark_store_width(ctx); mark_store_width(ctx);
} else { } else {
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
} }
} }
@ -912,7 +912,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
nwords = read_packet_words(env, ctx, words); nwords = read_packet_words(env, ctx, words);
if (!nwords) { if (!nwords) {
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
return; return;
} }
@ -927,7 +927,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
gen_commit_packet(ctx); gen_commit_packet(ctx);
ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
} else { } else {
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
} }
} }