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Initial support for SS-2 (Sun4c)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3870 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
7d85892b9b
commit
ee76f82edb
7 changed files with 438 additions and 8 deletions
202
hw/sun4m.c
202
hw/sun4m.c
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@ -1,5 +1,5 @@
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/*
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* QEMU Sun4m & Sun4d System Emulator
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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@ -51,6 +51,13 @@
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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@ -79,6 +86,7 @@ struct hwdef {
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target_phys_addr_t tcx_base, cs_base, power_base;
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target_phys_addr_t ecc_base;
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uint32_t ecc_version;
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target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller register
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// bit numbers
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@ -521,6 +529,142 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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ecc_init(hwdef->ecc_base, hwdef->ecc_version);
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}
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static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
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const char *boot_device,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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unsigned int i;
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void *iommu, *espdma, *ledma, *main_esp, *nvram;
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qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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unsigned long prom_offset, kernel_size;
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int ret;
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char buf[1024];
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BlockDriverState *fd[MAX_FD];
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int index;
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/* init CPU */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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cpu_sparc_set_id(env, 0);
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qemu_register_reset(main_cpu_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
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/* allocate RAM */
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if ((uint64_t)RAM_size > hwdef->max_mem) {
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fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
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(unsigned int)RAM_size / (1024 * 1024),
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(unsigned int)hwdef->max_mem / (1024 * 1024));
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exit(1);
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}
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cpu_register_physical_memory(0, RAM_size, 0);
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/* load boot prom */
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prom_offset = RAM_size + hwdef->vram_size;
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cpu_register_physical_memory(hwdef->slavio_base,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
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TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
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if (ret < 0 || ret > PROM_SIZE_MAX)
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ret = load_image(buf, phys_ram_base + prom_offset);
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if (ret < 0 || ret > PROM_SIZE_MAX) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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/* set up devices */
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slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
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&slavio_irq, cpu_irqs);
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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iommu, &espdma_irq, &esp_reset);
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ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
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slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
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&le_reset);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
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hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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} else if (strcmp(nd_table[0].model, "?") == 0) {
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fprintf(stderr, "qemu: Supported NICs: lance\n");
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exit (1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
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nographic);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
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serial_hds[1], serial_hds[0]);
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if (hwdef->fd_base != (target_phys_addr_t)-1) {
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/* there is zero or one floppy drive */
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fd[1] = fd[0] = NULL;
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index = drive_get_index(IF_FLOPPY, 0, 0);
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if (index != -1)
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fd[0] = drives_table[index].bdrv;
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sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
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}
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if (drive_get_max_bus(IF_SCSI) > 0) {
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fprintf(stderr, "qemu: too many SCSI bus\n");
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exit(1);
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}
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main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
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esp_reset);
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for (i = 0; i < ESP_MAX_DEVS; i++) {
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index = drive_get_index(IF_SCSI, 0, i);
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if (index == -1)
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continue;
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esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
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}
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kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
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initrd_filename);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
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}
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static const struct hwdef hwdefs[] = {
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/* SS-5 */
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{
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@ -540,6 +684,8 @@ static const struct hwdef hwdefs[] = {
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.le_base = 0x78c00000,
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.power_base = 0x7a000000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -579,6 +725,8 @@ static const struct hwdef hwdefs[] = {
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.power_base = 0xefa000000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x10000000, // version 0, implementation 1
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -618,6 +766,8 @@ static const struct hwdef hwdefs[] = {
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.power_base = 0xefa000000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x00000000, // version 0, implementation 0
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -657,6 +807,8 @@ static const struct hwdef hwdefs[] = {
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.power_base = 0xefa000000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x20000000, // version 0, implementation 2
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -677,6 +829,39 @@ static const struct hwdef hwdefs[] = {
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.max_mem = 0xffffffff, // XXX actually first 62GB ok
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.default_cpu_model = "TI SuperSparc II",
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},
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/* SS-2 */
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{
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.iommu_base = 0xf8000000,
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.tcx_base = 0xfe000000,
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.cs_base = -1,
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.slavio_base = 0xf6000000,
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.ms_kb_base = 0xf0000000,
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.serial_base = 0xf1000000,
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.nvram_base = 0xf2000000,
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.fd_base = 0xf7200000,
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.counter_base = -1,
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.intctl_base = -1,
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.dma_base = 0xf8400000,
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.esp_base = 0xf8800000,
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.le_base = 0xf8c00000,
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.power_base = -1,
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.sun4c_intctl_base = 0xf5000000,
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.sun4c_counter_base = 0xf3000000,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000, // XXX 0x800,
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.esp_irq = 2,
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.le_irq = 3,
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.clock_irq = 5,
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.clock1_irq = 7,
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.ms_kb_irq = 1,
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.ser_irq = 1,
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.fd_irq = 1,
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.me_irq = 1,
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.cs_irq = -1,
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.machine_id = 0x55,
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.max_mem = 0x10000000,
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.default_cpu_model = "Cypress CY7C601",
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},
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};
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/* SPARCstation 5 hardware initialisation */
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@ -719,6 +904,16 @@ static void ss20_init(int RAM_size, int vga_ram_size,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCstation 2 hardware initialisation */
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static void ss2_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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QEMUMachine ss5_machine = {
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"SS-5",
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"Sun4m platform, SPARCstation 5",
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@ -743,6 +938,11 @@ QEMUMachine ss20_machine = {
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ss20_init,
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};
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QEMUMachine ss2_machine = {
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"SS-2",
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"Sun4c platform, SPARCstation 2",
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ss2_init,
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};
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static const struct sun4d_hwdef sun4d_hwdefs[] = {
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/* SS-1000 */
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