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https://github.com/Motorhead1991/qemu.git
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* KVM error improvement from Laurent
* CONFIG_PARALLEL fix from Mirek * Atomic/optimized dirty bitmap access from myself and Stefan * BUILD_DIR convenience/bugfix from Peter C * Memory leak fix from Shannon * SMM improvements (though still TCG only) from myself and Gerd, acked by mst -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAABCAAGBQJVceAwAAoJEL/70l94x66Dyz4H/RHS/OUGo6HOwG1FZ4l8RxRl FY+pwJqinxFyGySmMLVHEeQCsIfxgi8bOmuWblG7sdt245nhMIj2jglyEOCUA3RN Q9qxQr6QyXBWiwK4bfB7xI1z3/mc8cVvuxjtkLaBMa16A4MXMunWCDcyhsX9/0Vw VySgTgBbn5AyY5x58TbkB7Tl6hMZgxF0yNwU6IGQvP079dgREAL2tzR1Wk8kPC80 ltLWlrwTAzF2km5m6rmstpMeZ/XIaq3DD2LU03SyUhefMsYowGKK+7Boo4lHpVm9 XAlxflahN7VGtQuno5RpYNNSzGqSJgqu5X5JxCMnbWdPi4sX3bijQdcUhW3/0oo= =KPIz -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * KVM error improvement from Laurent * CONFIG_PARALLEL fix from Mirek * Atomic/optimized dirty bitmap access from myself and Stefan * BUILD_DIR convenience/bugfix from Peter C * Memory leak fix from Shannon * SMM improvements (though still TCG only) from myself and Gerd, acked by mst # gpg: Signature made Fri Jun 5 18:45:20 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (62 commits) update Linux headers from kvm/next atomics: add explicit compiler fence in __atomic memory barriers ich9: implement SMI_LOCK q35: implement TSEG q35: add test for SMRAM.D_LCK q35: implement SMRAM.D_LCK q35: add config space wmask for SMRAM and ESMRAMC q35: fix ESMRAMC default q35: implement high SMRAM hw/i386: remove smram_update target-i386: use memory API to implement SMRAM hw/i386: add a separate region that tracks the SMRAME bit target-i386: create a separate AddressSpace for each CPU vl: run "late" notifiers immediately qom: add object_property_add_const_link vl: allow full-blown QemuOpts syntax for -global pflash_cfi01: add secure property pflash_cfi01: change to new-style MMIO accessors pflash_cfi01: change big-endian property to BIT type target-i386: wake up processors that receive an SMI ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
ee09f84e6b
75 changed files with 1548 additions and 1043 deletions
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@ -174,6 +174,8 @@ gcov-files-i386-y += hw/usb/dev-storage.c
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check-qtest-i386-y += tests/usb-hcd-xhci-test$(EXESUF)
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gcov-files-i386-y += hw/usb/hcd-xhci.c
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check-qtest-i386-y += tests/pc-cpu-test$(EXESUF)
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check-qtest-i386-y += tests/q35-test$(EXESUF)
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gcov-files-i386-y += hw/pci-host/q35.c
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check-qtest-i386-$(CONFIG_LINUX) += tests/vhost-user-test$(EXESUF)
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check-qtest-x86_64-y = $(check-qtest-i386-y)
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gcov-files-i386-y += i386-softmmu/hw/timer/mc146818rtc.c
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@ -355,6 +357,7 @@ tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
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tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y)
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tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
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tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
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tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
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tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
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tests/e1000-test$(EXESUF): tests/e1000-test.o
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tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y)
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91
tests/q35-test.c
Normal file
91
tests/q35-test.c
Normal file
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@ -0,0 +1,91 @@
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/*
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* QTest testcase for Q35 northbridge
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*
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* Copyright (c) 2015 Red Hat, Inc.
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*
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* Author: Gerd Hoffmann <kraxel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include <glib.h>
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#include <string.h>
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#include "libqtest.h"
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#include "libqos/pci.h"
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#include "libqos/pci-pc.h"
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#include "qemu/osdep.h"
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#include "hw/pci-host/q35.h"
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static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled)
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{
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uint8_t smram;
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smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
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if (enabled) {
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smram |= mask;
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} else {
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smram &= ~mask;
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}
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qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram);
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}
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static bool smram_test_bit(QPCIDevice *pcidev, uint8_t mask)
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{
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uint8_t smram;
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smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
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return smram & mask;
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}
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static void test_smram_lock(void)
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{
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QPCIBus *pcibus;
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QPCIDevice *pcidev;
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QDict *response;
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pcibus = qpci_init_pc();
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g_assert(pcibus != NULL);
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pcidev = qpci_device_find(pcibus, 0);
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g_assert(pcidev != NULL);
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/* check open is settable */
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
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/* lock, check open is cleared & not settable */
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_LCK, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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/* reset */
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response = qmp("{'execute': 'system_reset', 'arguments': {} }");
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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/* check open is settable again */
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
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}
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int main(int argc, char **argv)
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{
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int ret;
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/q35/smram/lock", test_smram_lock);
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qtest_start("-M q35");
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ret = g_test_run();
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qtest_end();
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return ret;
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}
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