mirror of
https://github.com/Motorhead1991/qemu.git
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pull-loongarch-20241102
-----BEGIN PGP SIGNATURE----- iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZyXbXgAKCRBAov/yOSY+ 37a9BADZ7vI2idWNXdH+mLNDZNSOxfdKp6ggNgKS3S48Hi2zR72MEhwvR9dGlHDL 98agrbV7/jI9Z+0dLAxvlyl1MvXfnn2sXYgUuZp6IAaQzFBa11HBAK7UFh3sTA4A gD4oPwl8AdJiFvDN6vNjS+dO0ls+j/YMaoLkAKLv15dlWtg4Rw== =EZnr -----END PGP SIGNATURE----- Merge tag 'pull-loongarch-20241102' of https://gitlab.com/gaosong/qemu into staging pull-loongarch-20241102 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZyXbXgAKCRBAov/yOSY+ # 37a9BADZ7vI2idWNXdH+mLNDZNSOxfdKp6ggNgKS3S48Hi2zR72MEhwvR9dGlHDL # 98agrbV7/jI9Z+0dLAxvlyl1MvXfnn2sXYgUuZp6IAaQzFBa11HBAK7UFh3sTA4A # gD4oPwl8AdJiFvDN6vNjS+dO0ls+j/YMaoLkAKLv15dlWtg4Rw== # =EZnr # -----END PGP SIGNATURE----- # gpg: Signature made Sat 02 Nov 2024 07:57:18 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20241102' of https://gitlab.com/gaosong/qemu: target/loongarch: Add steal time support on migration hw/loongarch/boot: Use warn_report when no kernel filename linux-headers: Update to Linux v6.12-rc5 linux-headers: loongarch: Add kvm_para.h linux-headers: Add unistd_64.h target/loongarch/kvm: Implement LoongArch PMU extension target/loongarch: Implement lbt registers save/restore function target/loongarch: Add loongson binary translation feature Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
ee057a9f29
36 changed files with 2243 additions and 100 deletions
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@ -664,12 +664,55 @@ static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
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}
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}
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static bool loongarch_get_lbt(Object *obj, Error **errp)
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{
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return LOONGARCH_CPU(obj)->lbt != ON_OFF_AUTO_OFF;
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}
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static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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cpu->lbt = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
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}
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static bool loongarch_get_pmu(Object *obj, Error **errp)
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{
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return LOONGARCH_CPU(obj)->pmu != ON_OFF_AUTO_OFF;
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}
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static void loongarch_set_pmu(Object *obj, bool value, Error **errp)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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cpu->pmu = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
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}
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void loongarch_cpu_post_init(Object *obj)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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object_property_add_bool(obj, "lsx", loongarch_get_lsx,
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loongarch_set_lsx);
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object_property_add_bool(obj, "lasx", loongarch_get_lasx,
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loongarch_set_lasx);
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/* lbt is enabled only in kvm mode, not supported in tcg mode */
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if (kvm_enabled()) {
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cpu->lbt = ON_OFF_AUTO_AUTO;
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object_property_add_bool(obj, "lbt", loongarch_get_lbt,
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loongarch_set_lbt);
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object_property_set_description(obj, "lbt",
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"Set off to disable Binary Tranlation.");
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cpu->pmu = ON_OFF_AUTO_AUTO;
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object_property_add_bool(obj, "pmu", loongarch_get_pmu,
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loongarch_set_pmu);
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object_property_set_description(obj, "pmu",
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"Set off to performance monitor unit.");
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} else {
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cpu->lbt = ON_OFF_AUTO_OFF;
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}
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}
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static void loongarch_cpu_init(Object *obj)
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@ -153,6 +153,7 @@ FIELD(CPUCFG2, LLFTP_VER, 15, 3)
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FIELD(CPUCFG2, LBT_X86, 18, 1)
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FIELD(CPUCFG2, LBT_ARM, 19, 1)
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FIELD(CPUCFG2, LBT_MIPS, 20, 1)
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FIELD(CPUCFG2, LBT_ALL, 18, 3)
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FIELD(CPUCFG2, LSPW, 21, 1)
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FIELD(CPUCFG2, LAM, 22, 1)
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@ -281,6 +282,22 @@ struct LoongArchTLB {
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typedef struct LoongArchTLB LoongArchTLB;
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#endif
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enum loongarch_features {
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LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
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LOONGARCH_FEATURE_PMU,
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};
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typedef struct LoongArchBT {
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/* scratch registers */
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uint64_t scr0;
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uint64_t scr1;
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uint64_t scr2;
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uint64_t scr3;
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/* loongarch eflags */
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uint32_t eflags;
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uint32_t ftop;
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} lbt_t;
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typedef struct CPUArchState {
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uint64_t gpr[32];
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uint64_t pc;
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@ -288,6 +305,7 @@ typedef struct CPUArchState {
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fpr_t fpr[32];
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bool cf[8];
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uint32_t fcsr0;
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lbt_t lbt;
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uint32_t cpucfg[21];
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@ -346,6 +364,9 @@ typedef struct CPUArchState {
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uint64_t CSR_DBG;
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uint64_t CSR_DERA;
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uint64_t CSR_DSAVE;
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struct {
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uint64_t guest_addr;
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} stealtime;
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#ifdef CONFIG_TCG
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float_status fp_status;
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@ -381,6 +402,8 @@ struct ArchCPU {
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CPULoongArchState env;
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QEMUTimer timer;
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uint32_t phy_id;
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OnOffAuto lbt;
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OnOffAuto pmu;
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/* 'compatible' string for this CPU for Linux device trees */
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const char *dtb_compatible;
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@ -9,6 +9,7 @@
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#include <sys/ioctl.h>
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#include <linux/kvm.h>
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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@ -33,6 +34,55 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_LAST_INFO
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};
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static int kvm_get_stealtime(CPUState *cs)
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{
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CPULoongArchState *env = cpu_env(cs);
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int err;
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struct kvm_device_attr attr = {
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.group = KVM_LOONGARCH_VCPU_PVTIME_CTRL,
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.attr = KVM_LOONGARCH_VCPU_PVTIME_GPA,
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.addr = (uint64_t)&env->stealtime.guest_addr,
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};
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err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
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if (err) {
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return 0;
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}
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err = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, attr);
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if (err) {
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error_report("PVTIME: KVM_GET_DEVICE_ATTR: %s", strerror(errno));
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return err;
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}
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return 0;
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}
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static int kvm_set_stealtime(CPUState *cs)
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{
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CPULoongArchState *env = cpu_env(cs);
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int err;
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struct kvm_device_attr attr = {
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.group = KVM_LOONGARCH_VCPU_PVTIME_CTRL,
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.attr = KVM_LOONGARCH_VCPU_PVTIME_GPA,
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.addr = (uint64_t)&env->stealtime.guest_addr,
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};
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err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
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if (err) {
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return 0;
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}
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err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
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if (err) {
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error_report("PVTIME: KVM_SET_DEVICE_ATTR %s with gpa "TARGET_FMT_lx,
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strerror(errno), env->stealtime.guest_addr);
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return err;
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}
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return 0;
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}
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static int kvm_loongarch_get_regs_core(CPUState *cs)
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{
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int ret = 0;
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@ -476,6 +526,58 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs)
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return ret;
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}
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static int kvm_loongarch_put_lbt(CPUState *cs)
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{
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CPULoongArchState *env = cpu_env(cs);
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uint64_t val;
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int ret;
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/* check whether vm support LBT firstly */
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) {
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return 0;
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}
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/* set six LBT registers including scr0-scr3, eflags, ftop */
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ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0);
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ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1);
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ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2);
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ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3);
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/*
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* Be cautious, KVM_REG_LOONGARCH_LBT_FTOP is defined as 64-bit however
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* lbt.ftop is 32-bit; the same with KVM_REG_LOONGARCH_LBT_EFLAGS register
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*/
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val = env->lbt.eflags;
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ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &val);
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val = env->lbt.ftop;
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ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val);
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return ret;
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}
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static int kvm_loongarch_get_lbt(CPUState *cs)
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{
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CPULoongArchState *env = cpu_env(cs);
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uint64_t val;
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int ret;
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/* check whether vm support LBT firstly */
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) {
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return 0;
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}
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/* get six LBT registers including scr0-scr3, eflags, ftop */
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ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0);
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ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1);
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ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2);
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ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3);
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ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &val);
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env->lbt.eflags = (uint32_t)val;
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ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val);
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env->lbt.ftop = (uint32_t)val;
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return ret;
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}
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void kvm_arch_reset_vcpu(CPUState *cs)
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{
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CPULoongArchState *env = cpu_env(cs);
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@ -612,6 +714,16 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)
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return ret;
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}
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ret = kvm_loongarch_get_lbt(cs);
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if (ret) {
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return ret;
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}
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ret = kvm_get_stealtime(cs);
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if (ret) {
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return ret;
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}
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ret = kvm_loongarch_get_mpstate(cs);
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return ret;
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}
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@ -640,6 +752,22 @@ int kvm_arch_put_registers(CPUState *cs, int level, Error **errp)
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return ret;
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}
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ret = kvm_loongarch_put_lbt(cs);
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if (ret) {
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return ret;
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}
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if (level >= KVM_PUT_FULL_STATE) {
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/*
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* only KVM_PUT_FULL_STATE is required, kvm kernel will clear
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* guest_addr for KVM_PUT_RESET_STATE
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*/
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ret = kvm_set_stealtime(cs);
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if (ret) {
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return ret;
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}
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}
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ret = kvm_loongarch_put_mpstate(cs);
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return ret;
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}
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@ -666,17 +794,112 @@ static void kvm_loongarch_vm_stage_change(void *opaque, bool running,
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}
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}
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static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
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{
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int ret;
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struct kvm_device_attr attr;
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switch (feature) {
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case LOONGARCH_FEATURE_LBT:
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/*
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* Return all if all the LBT features are supported such as:
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* KVM_LOONGARCH_VM_FEAT_X86BT
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* KVM_LOONGARCH_VM_FEAT_ARMBT
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* KVM_LOONGARCH_VM_FEAT_MIPSBT
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*/
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attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
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attr.attr = KVM_LOONGARCH_VM_FEAT_X86BT;
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ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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attr.attr = KVM_LOONGARCH_VM_FEAT_ARMBT;
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ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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attr.attr = KVM_LOONGARCH_VM_FEAT_MIPSBT;
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ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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return (ret == 0);
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case LOONGARCH_FEATURE_PMU:
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attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
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attr.attr = KVM_LOONGARCH_VM_FEAT_PMU;
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ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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return (ret == 0);
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default:
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return false;
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}
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return false;
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}
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static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
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{
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CPULoongArchState *env = cpu_env(cs);
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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bool kvm_supported;
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kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LBT);
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if (cpu->lbt == ON_OFF_AUTO_ON) {
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if (kvm_supported) {
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env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7);
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} else {
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error_setg(errp, "'lbt' feature not supported by KVM on this host");
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return -ENOTSUP;
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}
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} else if ((cpu->lbt == ON_OFF_AUTO_AUTO) && kvm_supported) {
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env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7);
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}
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return 0;
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}
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static int kvm_cpu_check_pmu(CPUState *cs, Error **errp)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = cpu_env(cs);
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bool kvm_supported;
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kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_PMU);
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if (cpu->pmu == ON_OFF_AUTO_ON) {
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if (!kvm_supported) {
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error_setg(errp, "'pmu' feature not supported by KVM on the host");
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return -ENOTSUP;
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}
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} else if (cpu->pmu != ON_OFF_AUTO_AUTO) {
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/* disable pmu if ON_OFF_AUTO_OFF is set */
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kvm_supported = false;
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}
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if (kvm_supported) {
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env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, PMP, 1);
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env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, PMNUM, 3);
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env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, PMBITS, 63);
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env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, UPM, 1);
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}
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return 0;
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}
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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uint64_t val;
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int ret;
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Error *local_err = NULL;
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ret = 0;
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qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs);
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if (!kvm_get_one_reg(cs, KVM_REG_LOONGARCH_DEBUG_INST, &val)) {
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brk_insn = val;
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}
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return 0;
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ret = kvm_cpu_check_lbt(cs, &local_err);
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if (ret < 0) {
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error_report_err(local_err);
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}
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ret = kvm_cpu_check_pmu(cs, &local_err);
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if (ret < 0) {
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error_report_err(local_err);
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}
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return ret;
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}
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int kvm_arch_destroy_vcpu(CPUState *cs)
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|
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|||
|
|
@ -40,7 +40,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
|
|||
}
|
||||
|
||||
static const char *cpu_model_advertised_features[] = {
|
||||
"lsx", "lasx", NULL
|
||||
"lsx", "lasx", "lbt", "pmu", NULL
|
||||
};
|
||||
|
||||
CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
|
||||
|
|
|
|||
|
|
@ -110,6 +110,29 @@ static const VMStateDescription vmstate_lasx = {
|
|||
},
|
||||
};
|
||||
|
||||
static bool lbt_needed(void *opaque)
|
||||
{
|
||||
LoongArchCPU *cpu = opaque;
|
||||
|
||||
return !!FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_lbt = {
|
||||
.name = "cpu/lbt",
|
||||
.version_id = 0,
|
||||
.minimum_version_id = 0,
|
||||
.needed = lbt_needed,
|
||||
.fields = (const VMStateField[]) {
|
||||
VMSTATE_UINT64(env.lbt.scr0, LoongArchCPU),
|
||||
VMSTATE_UINT64(env.lbt.scr1, LoongArchCPU),
|
||||
VMSTATE_UINT64(env.lbt.scr2, LoongArchCPU),
|
||||
VMSTATE_UINT64(env.lbt.scr3, LoongArchCPU),
|
||||
VMSTATE_UINT32(env.lbt.eflags, LoongArchCPU),
|
||||
VMSTATE_UINT32(env.lbt.ftop, LoongArchCPU),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
};
|
||||
|
||||
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
|
||||
static bool tlb_needed(void *opaque)
|
||||
{
|
||||
|
|
@ -145,8 +168,8 @@ static const VMStateDescription vmstate_tlb = {
|
|||
/* LoongArch CPU state */
|
||||
const VMStateDescription vmstate_loongarch_cpu = {
|
||||
.name = "cpu",
|
||||
.version_id = 2,
|
||||
.minimum_version_id = 2,
|
||||
.version_id = 3,
|
||||
.minimum_version_id = 3,
|
||||
.fields = (const VMStateField[]) {
|
||||
VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
|
||||
VMSTATE_UINTTL(env.pc, LoongArchCPU),
|
||||
|
|
@ -209,6 +232,8 @@ const VMStateDescription vmstate_loongarch_cpu = {
|
|||
VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
|
||||
|
||||
VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
|
||||
/* PV steal time */
|
||||
VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU),
|
||||
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
|
|
@ -219,6 +244,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
|
|||
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
|
||||
&vmstate_tlb,
|
||||
#endif
|
||||
&vmstate_lbt,
|
||||
NULL
|
||||
}
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue