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hw/arm: Replace TABs for spaces in OMAP board and device code
In hw/arm and include/hw/arm, some source files for the OMAP SoC and the sx1 boards that are our only remaining OMAP boards still have hard-coded tabs (almost entirely used for the indent on inline comments, not for actual code indent). Replace the tabs with spaces using vim :retab. I used 4 spaces except in some defines and comments where I tried to put everything aligned in the same column for better readability. This commit is a purely whitespace-only change. Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> Message-id: 20250505131130.82206-1-santimonserr@gmail.com Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373 [PMM: expanded commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Santiago Monserrat Campanello
Peter Maydell
parent
6414b7709d
commit
edf838289b
11 changed files with 1399 additions and 1399 deletions
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@ -55,16 +55,16 @@ struct OMAPI2CState {
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uint16_t test;
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};
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#define OMAP2_INTR_REV 0x34
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#define OMAP2_GC_REV 0x34
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#define OMAP2_INTR_REV 0x34
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#define OMAP2_GC_REV 0x34
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static void omap_i2c_interrupts_update(OMAPI2CState *s)
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{
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qemu_set_irq(s->irq, s->stat & s->mask);
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if ((s->dma >> 15) & 1) /* RDMA_EN */
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qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
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if ((s->dma >> 7) & 1) /* XDMA_EN */
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qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
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if ((s->dma >> 15) & 1) /* RDMA_EN */
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qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
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if ((s->dma >> 7) & 1) /* XDMA_EN */
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qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
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}
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static void omap_i2c_fifo_run(OMAPI2CState *s)
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@ -74,25 +74,25 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
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if (!i2c_bus_busy(s->bus))
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return;
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if ((s->control >> 2) & 1) { /* RM */
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if ((s->control >> 1) & 1) { /* STP */
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if ((s->control >> 2) & 1) { /* RM */
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if ((s->control >> 1) & 1) { /* STP */
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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s->txlen = 0;
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} else if ((s->control >> 9) & 1) { /* TRX */
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} else if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->txlen)
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ack = (i2c_send(s->bus,
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0);
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s->stat |= 1 << 4; /* XRDY */
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s->stat |= 1 << 4; /* XRDY */
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} else {
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while (s->rxlen < 4)
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->stat |= 1 << 3; /* RRDY */
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s->stat |= 1 << 3; /* RRDY */
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}
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} else {
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if ((s->control >> 9) & 1) { /* TRX */
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if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->count_cur && s->txlen) {
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ack = (i2c_send(s->bus,
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(s->fifo >> ((-- s->txlen) << 3)) &
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@ -100,12 +100,12 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
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s->count_cur --;
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}
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if (ack && s->count_cur)
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s->stat |= 1 << 4; /* XRDY */
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s->stat |= 1 << 4; /* XRDY */
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else
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s->stat &= ~(1 << 4); /* XRDY */
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s->stat &= ~(1 << 4); /* XRDY */
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if (!s->count_cur) {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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} else {
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while (s->count_cur && s->rxlen < 4) {
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@ -113,26 +113,26 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
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s->count_cur --;
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}
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if (s->rxlen)
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s->stat |= 1 << 3; /* RRDY */
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s->stat |= 1 << 3; /* RRDY */
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else
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s->stat &= ~(1 << 3); /* RRDY */
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s->stat &= ~(1 << 3); /* RRDY */
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}
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if (!s->count_cur) {
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if ((s->control >> 1) & 1) { /* STP */
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if ((s->control >> 1) & 1) { /* STP */
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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s->txlen = 0;
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} else {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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}
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}
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s->stat |= (!ack) << 1; /* NACK */
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s->stat |= (!ack) << 1; /* NACK */
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if (!ack)
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s->control &= ~(1 << 1); /* STP */
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s->control &= ~(1 << 1); /* STP */
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}
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static void omap_i2c_reset(DeviceState *dev)
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@ -163,16 +163,16 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
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uint16_t ret;
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switch (offset) {
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case 0x00: /* I2C_REV */
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return s->revision; /* REV */
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case 0x00: /* I2C_REV */
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return s->revision; /* REV */
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case 0x04: /* I2C_IE */
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case 0x04: /* I2C_IE */
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return s->mask;
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case 0x08: /* I2C_STAT */
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case 0x08: /* I2C_STAT */
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return s->stat | (i2c_bus_busy(s->bus) << 12);
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case 0x0c: /* I2C_IV */
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case 0x0c: /* I2C_IV */
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if (s->revision >= OMAP2_INTR_REV)
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break;
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ret = ctz32(s->stat & s->mask);
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@ -185,18 +185,18 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x10: /* I2C_SYSS */
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return (s->control >> 15) & 1; /* I2C_EN */
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case 0x10: /* I2C_SYSS */
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return (s->control >> 15) & 1; /* I2C_EN */
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case 0x14: /* I2C_BUF */
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case 0x14: /* I2C_BUF */
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return s->dma;
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case 0x18: /* I2C_CNT */
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return s->count_cur; /* DCOUNT */
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case 0x18: /* I2C_CNT */
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return s->count_cur; /* DCOUNT */
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case 0x1c: /* I2C_DATA */
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case 0x1c: /* I2C_DATA */
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ret = 0;
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if (s->control & (1 << 14)) { /* BE */
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if (s->control & (1 << 14)) { /* BE */
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ret |= ((s->fifo >> 0) & 0xff) << 8;
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ret |= ((s->fifo >> 8) & 0xff) << 0;
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} else {
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@ -204,7 +204,7 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
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ret |= ((s->fifo >> 0) & 0xff) << 0;
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}
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if (s->rxlen == 1) {
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s->stat |= 1 << 15; /* SBD */
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s->stat |= 1 << 15; /* SBD */
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s->rxlen = 0;
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} else if (s->rxlen > 1) {
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if (s->rxlen > 2)
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@ -214,41 +214,41 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
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/* XXX: remote access (qualifier) error - what's that? */
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}
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if (!s->rxlen) {
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s->stat &= ~(1 << 3); /* RRDY */
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if (((s->control >> 10) & 1) && /* MST */
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((~s->control >> 9) & 1)) { /* TRX */
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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s->stat &= ~(1 << 3); /* RRDY */
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if (((s->control >> 10) & 1) && /* MST */
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((~s->control >> 9) & 1)) { /* TRX */
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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}
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s->stat &= ~(1 << 11); /* ROVR */
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s->stat &= ~(1 << 11); /* ROVR */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x20: /* I2C_SYSC */
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case 0x20: /* I2C_SYSC */
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return 0;
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case 0x24: /* I2C_CON */
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case 0x24: /* I2C_CON */
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return s->control;
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case 0x28: /* I2C_OA */
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case 0x28: /* I2C_OA */
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return s->addr[0];
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case 0x2c: /* I2C_SA */
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case 0x2c: /* I2C_SA */
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return s->addr[1];
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case 0x30: /* I2C_PSC */
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case 0x30: /* I2C_PSC */
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return s->divider;
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case 0x34: /* I2C_SCLL */
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case 0x34: /* I2C_SCLL */
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return s->times[0];
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case 0x38: /* I2C_SCLH */
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case 0x38: /* I2C_SCLH */
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return s->times[1];
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case 0x3c: /* I2C_SYSTEST */
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if (s->test & (1 << 15)) { /* ST_EN */
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case 0x3c: /* I2C_SYSTEST */
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if (s->test & (1 << 15)) { /* ST_EN */
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s->test ^= 0xa;
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return s->test;
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} else
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@ -267,17 +267,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
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int nack;
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switch (offset) {
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case 0x00: /* I2C_REV */
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case 0x0c: /* I2C_IV */
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case 0x10: /* I2C_SYSS */
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case 0x00: /* I2C_REV */
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case 0x0c: /* I2C_IV */
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case 0x10: /* I2C_SYSS */
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OMAP_RO_REG(addr);
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return;
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case 0x04: /* I2C_IE */
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case 0x04: /* I2C_IE */
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s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
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break;
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case 0x08: /* I2C_STAT */
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case 0x08: /* I2C_STAT */
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_RO_REG(addr);
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return;
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@ -288,40 +288,40 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
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omap_i2c_interrupts_update(s);
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break;
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case 0x14: /* I2C_BUF */
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case 0x14: /* I2C_BUF */
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s->dma = value & 0x8080;
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if (value & (1 << 15)) /* RDMA_EN */
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s->mask &= ~(1 << 3); /* RRDY_IE */
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if (value & (1 << 7)) /* XDMA_EN */
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s->mask &= ~(1 << 4); /* XRDY_IE */
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if (value & (1 << 15)) /* RDMA_EN */
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s->mask &= ~(1 << 3); /* RRDY_IE */
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if (value & (1 << 7)) /* XDMA_EN */
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s->mask &= ~(1 << 4); /* XRDY_IE */
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break;
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case 0x18: /* I2C_CNT */
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s->count = value; /* DCOUNT */
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case 0x18: /* I2C_CNT */
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s->count = value; /* DCOUNT */
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break;
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case 0x1c: /* I2C_DATA */
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case 0x1c: /* I2C_DATA */
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if (s->txlen > 2) {
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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}
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s->fifo <<= 16;
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s->txlen += 2;
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if (s->control & (1 << 14)) { /* BE */
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if (s->control & (1 << 14)) { /* BE */
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s->fifo |= ((value >> 8) & 0xff) << 8;
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s->fifo |= ((value >> 0) & 0xff) << 0;
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} else {
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s->fifo |= ((value >> 0) & 0xff) << 8;
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s->fifo |= ((value >> 8) & 0xff) << 0;
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}
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s->stat &= ~(1 << 10); /* XUDF */
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s->stat &= ~(1 << 10); /* XUDF */
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if (s->txlen > 2)
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s->stat &= ~(1 << 4); /* XRDY */
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s->stat &= ~(1 << 4); /* XRDY */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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break;
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case 0x20: /* I2C_SYSC */
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case 0x20: /* I2C_SYSC */
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_BAD_REG(addr);
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return;
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@ -332,9 +332,9 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
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}
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break;
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case 0x24: /* I2C_CON */
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case 0x24: /* I2C_CON */
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s->control = value & 0xcf87;
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if (~value & (1 << 15)) { /* I2C_EN */
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if (~value & (1 << 15)) { /* I2C_EN */
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if (s->revision < OMAP2_INTR_REV) {
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omap_i2c_reset(DEVICE(s));
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}
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@ -351,14 +351,14 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
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__func__);
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break;
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}
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if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
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nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
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(~value >> 9) & 1); /* TRX */
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s->stat |= nack << 1; /* NACK */
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s->control &= ~(1 << 0); /* STT */
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if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
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nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
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(~value >> 9) & 1); /* TRX */
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s->stat |= nack << 1; /* NACK */
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s->control &= ~(1 << 0); /* STT */
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s->fifo = 0;
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if (nack)
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s->control &= ~(1 << 1); /* STP */
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s->control &= ~(1 << 1); /* STP */
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else {
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s->count_cur = s->count;
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omap_i2c_fifo_run(s);
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@ -367,34 +367,34 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
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}
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break;
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case 0x28: /* I2C_OA */
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case 0x28: /* I2C_OA */
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s->addr[0] = value & 0x3ff;
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break;
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case 0x2c: /* I2C_SA */
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case 0x2c: /* I2C_SA */
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s->addr[1] = value & 0x3ff;
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break;
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case 0x30: /* I2C_PSC */
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case 0x30: /* I2C_PSC */
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s->divider = value;
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break;
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case 0x34: /* I2C_SCLL */
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case 0x34: /* I2C_SCLL */
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s->times[0] = value;
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break;
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case 0x38: /* I2C_SCLH */
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case 0x38: /* I2C_SCLH */
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s->times[1] = value;
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break;
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case 0x3c: /* I2C_SYSTEST */
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case 0x3c: /* I2C_SYSTEST */
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s->test = value & 0xf80f;
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if (value & (1 << 11)) /* SBB */
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if (value & (1 << 11)) /* SBB */
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if (s->revision >= OMAP2_INTR_REV) {
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s->stat |= 0x3f;
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omap_i2c_interrupts_update(s);
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}
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if (value & (1 << 15)) { /* ST_EN */
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if (value & (1 << 15)) { /* ST_EN */
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qemu_log_mask(LOG_UNIMP,
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"%s: System Test not supported\n", __func__);
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}
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@ -413,7 +413,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x1c: /* I2C_DATA */
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case 0x1c: /* I2C_DATA */
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if (s->txlen > 2) {
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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@ -421,9 +421,9 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
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s->fifo <<= 8;
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s->txlen += 1;
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s->fifo |= value & 0xff;
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s->stat &= ~(1 << 10); /* XUDF */
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s->stat &= ~(1 << 10); /* XUDF */
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if (s->txlen > 2)
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s->stat &= ~(1 << 4); /* XRDY */
|
||||
s->stat &= ~(1 << 4); /* XRDY */
|
||||
omap_i2c_fifo_run(s);
|
||||
omap_i2c_interrupts_update(s);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue