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include/hw/pci: Split pci_device.h off pci.h
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Markus Armbruster
Michael S. Tsirkin
parent
4a96b8cf49
commit
edf5ca5dbe
93 changed files with 441 additions and 427 deletions
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@ -22,7 +22,7 @@
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#ifndef HW_ACPI_PIIX4_H
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#define HW_ACPI_PIIX4_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/cpu_hotplug.h"
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#include "hw/acpi/memory_hotplug.h"
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@ -4,6 +4,7 @@
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#include "qemu/error-report.h"
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#include "hw/char/serial.h"
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#include "hw/arm/boot.h"
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#include "hw/pci/pci_device.h"
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#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/intc/allwinner-a10-pic.h"
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#include "hw/net/allwinner_emac.h"
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@ -11,7 +11,7 @@
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#define CXL_DEVICE_H
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#include "hw/cxl/cxl_component.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/register.h"
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/*
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@ -2,7 +2,7 @@
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#define HW_IDE_PCI_H
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#include "hw/ide/internal.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "qom/object.h"
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#define BM_STATUS_DMAING 0x01
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@ -27,7 +27,7 @@
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#define MACIO_H
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#include "hw/char/escc.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/ide/internal.h"
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#include "hw/intc/heathrow_pic.h"
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#include "hw/misc/macio/cuda.h"
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@ -22,7 +22,7 @@
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#include "exec/hwaddr.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci/pcie_host.h"
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#include "qom/object.h"
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@ -11,7 +11,7 @@
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#ifndef HW_PCI_I440FX_H
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#define HW_PCI_I440FX_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci-host/pam.h"
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#include "qom/object.h"
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@ -22,7 +22,7 @@
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#ifndef HW_Q35_H
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#define HW_Q35_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci-host/pam.h"
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#include "qemu/units.h"
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@ -1,7 +1,7 @@
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#ifndef HW_PCI_HOST_SABRE_H
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#define HW_PCI_HOST_SABRE_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci/pci_host.h"
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#include "hw/sparc/sun4u_iommu.h"
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#include "qom/object.h"
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@ -21,7 +21,7 @@
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#ifndef QEMU_MSI_H
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#define QEMU_MSI_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_device.h"
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struct MSIMessage {
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uint64_t address;
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@ -166,7 +166,6 @@ enum {
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#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
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#include "hw/pci/pci_regs.h"
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#include "hw/pci/pcie.h"
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/* PCI HEADER_TYPE */
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#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
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@ -210,23 +209,6 @@ enum {
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QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
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};
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#define TYPE_PCI_DEVICE "pci-device"
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typedef struct PCIDeviceClass PCIDeviceClass;
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DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
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PCI_DEVICE, TYPE_PCI_DEVICE)
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/*
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* Implemented by devices that can be plugged on CXL buses. In the spec, this is
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* actually a "CXL Component, but we name it device to match the PCI naming.
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*/
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#define INTERFACE_CXL_DEVICE "cxl-device"
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/* Implemented by devices that can be plugged on PCI Express buses */
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#define INTERFACE_PCIE_DEVICE "pci-express-device"
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/* Implemented by devices that can be plugged on Conventional PCI buses */
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#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
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typedef struct PCIINTxRoute {
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enum {
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PCI_INTX_ENABLED,
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@ -236,24 +218,6 @@ typedef struct PCIINTxRoute {
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int irq;
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} PCIINTxRoute;
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struct PCIDeviceClass {
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DeviceClass parent_class;
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void (*realize)(PCIDevice *dev, Error **errp);
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PCIUnregisterFunc *exit;
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision;
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uint16_t class_id;
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uint16_t subsystem_vendor_id; /* only for header type = 0 */
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uint16_t subsystem_id; /* only for header type = 0 */
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const char *romfile; /* rom bar */
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};
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typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
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typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
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MSIMessage msg);
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@ -262,129 +226,6 @@ typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
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unsigned int vector_start,
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unsigned int vector_end);
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enum PCIReqIDType {
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PCI_REQ_ID_INVALID = 0,
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PCI_REQ_ID_BDF,
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PCI_REQ_ID_SECONDARY_BUS,
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PCI_REQ_ID_MAX,
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};
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typedef enum PCIReqIDType PCIReqIDType;
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struct PCIReqIDCache {
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PCIDevice *dev;
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PCIReqIDType type;
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};
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typedef struct PCIReqIDCache PCIReqIDCache;
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struct PCIDevice {
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DeviceState qdev;
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bool partially_hotplugged;
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bool has_power;
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/* PCI config space */
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uint8_t *config;
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/*
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* Used to enable config checks on load. Note that writable bits are
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* never checked even if set in cmask.
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*/
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uint8_t *cmask;
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/* Used to implement R/W bytes */
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uint8_t *wmask;
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/* Used to implement RW1C(Write 1 to Clear) bytes */
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uint8_t *w1cmask;
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/* Used to allocate config space for capabilities. */
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uint8_t *used;
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/* the following fields are read only */
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int32_t devfn;
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/*
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* Cached device to fetch requester ID from, to avoid the PCI tree
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* walking every time we invoke PCI request (e.g., MSI). For
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* conventional PCI root complex, this field is meaningless.
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*/
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PCIReqIDCache requester_id_cache;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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AddressSpace bus_master_as;
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MemoryRegion bus_master_container_region;
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MemoryRegion bus_master_enable_region;
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/* Legacy PCI VGA regions */
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MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
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bool has_vga;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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uint8_t irq_state;
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/* Capability bits */
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uint32_t cap_present;
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/* Offset of MSI-X capability in config space */
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uint8_t msix_cap;
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/* MSI-X entries */
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int msix_entries_nr;
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/* Space to store MSIX table & pending bit array */
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uint8_t *msix_table;
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uint8_t *msix_pba;
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/* May be used by INTx or MSI during interrupt notification */
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void *irq_opaque;
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MSITriggerFunc *msi_trigger;
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MSIPrepareMessageFunc *msi_prepare_message;
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MSIxPrepareMessageFunc *msix_prepare_message;
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/* MemoryRegion container for msix exclusive BAR setup */
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MemoryRegion msix_exclusive_bar;
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/* Memory Regions for MSIX table and pending bit entries. */
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MemoryRegion msix_table_mmio;
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MemoryRegion msix_pba_mmio;
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/* Reference-count for entries actually in use by driver. */
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unsigned *msix_entry_used;
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/* MSIX function mask set or MSIX disabled */
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bool msix_function_masked;
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/* Version id needed for VMState */
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int32_t version_id;
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/* Offset of MSI capability in config space */
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uint8_t msi_cap;
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/* PCI Express */
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PCIExpressDevice exp;
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/* SHPC */
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SHPCDevice *shpc;
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/* Location of option rom */
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char *romfile;
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uint32_t romsize;
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bool has_rom;
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MemoryRegion rom;
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uint32_t rom_bar;
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/* INTx routing notifier */
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PCIINTxRoutingNotifier intx_routing_notifier;
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/* MSI-X notifiers */
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MSIVectorUseNotifier msix_vector_use_notifier;
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MSIVectorReleaseNotifier msix_vector_release_notifier;
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MSIVectorPollNotifier msix_vector_poll_notifier;
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/* ID of standby device in net_failover pair */
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char *failover_pair_id;
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uint32_t acpi_index;
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};
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void pci_register_bar(PCIDevice *pci_dev, int region_num,
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uint8_t attr, MemoryRegion *memory);
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void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
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@ -745,11 +586,6 @@ void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
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qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
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void pci_set_irq(PCIDevice *pci_dev, int level);
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static inline int pci_intx(PCIDevice *pci_dev)
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{
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return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
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}
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static inline void pci_irq_assert(PCIDevice *pci_dev)
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{
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pci_set_irq(pci_dev, 1);
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@ -770,186 +606,6 @@ static inline void pci_irq_pulse(PCIDevice *pci_dev)
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pci_irq_deassert(pci_dev);
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}
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static inline int pci_is_cxl(const PCIDevice *d)
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{
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return d->cap_present & QEMU_PCIE_CAP_CXL;
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}
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static inline int pci_is_express(const PCIDevice *d)
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{
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return d->cap_present & QEMU_PCI_CAP_EXPRESS;
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}
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static inline int pci_is_express_downstream_port(const PCIDevice *d)
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{
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uint8_t type;
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if (!pci_is_express(d) || !d->exp.exp_cap) {
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return 0;
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}
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type = pcie_cap_get_type(d);
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return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
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}
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static inline int pci_is_vf(const PCIDevice *d)
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{
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return d->exp.sriov_vf.pf != NULL;
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}
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static inline uint32_t pci_config_size(const PCIDevice *d)
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{
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return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
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}
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static inline uint16_t pci_get_bdf(PCIDevice *dev)
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{
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return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
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}
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uint16_t pci_requester_id(PCIDevice *dev);
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/* DMA access functions */
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static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
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{
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return &dev->bus_master_as;
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}
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/**
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* pci_dma_rw: Read from or write to an address space from PCI device.
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*
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* Return a MemTxResult indicating whether the operation succeeded
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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* @dev: #PCIDevice doing the memory access
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* @addr: address within the #PCIDevice address space
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* @buf: buffer with the data transferred
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* @len: the number of bytes to read or write
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* @dir: indicates the transfer direction
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*/
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static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
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void *buf, dma_addr_t len,
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DMADirection dir, MemTxAttrs attrs)
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{
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return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
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dir, attrs);
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}
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/**
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* pci_dma_read: Read from an address space from PCI device.
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*
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* Return a MemTxResult indicating whether the operation succeeded
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault). Called within RCU critical section.
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*
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* @dev: #PCIDevice doing the memory access
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* @addr: address within the #PCIDevice address space
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* @buf: buffer with the data transferred
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* @len: length of the data transferred
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*/
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static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
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void *buf, dma_addr_t len)
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{
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return pci_dma_rw(dev, addr, buf, len,
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DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
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}
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/**
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* pci_dma_write: Write to address space from PCI device.
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*
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* Return a MemTxResult indicating whether the operation succeeded
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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* @dev: #PCIDevice doing the memory access
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* @addr: address within the #PCIDevice address space
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* @buf: buffer with the data transferred
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* @len: the number of bytes to write
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*/
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static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
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const void *buf, dma_addr_t len)
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{
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return pci_dma_rw(dev, addr, (void *) buf, len,
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DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
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}
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#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
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static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
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dma_addr_t addr, \
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uint##_bits##_t *val, \
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MemTxAttrs attrs) \
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{ \
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return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
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} \
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static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
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dma_addr_t addr, \
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uint##_bits##_t val, \
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MemTxAttrs attrs) \
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{ \
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return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
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}
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PCI_DMA_DEFINE_LDST(ub, b, 8);
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PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
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PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
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PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
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PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
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PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
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PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
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#undef PCI_DMA_DEFINE_LDST
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/**
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* pci_dma_map: Map device PCI address space range into host virtual address
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* @dev: #PCIDevice to be accessed
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* @addr: address within that device's address space
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* @plen: pointer to length of buffer; updated on return to indicate
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* if only a subset of the requested range has been mapped
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* @dir: indicates the transfer direction
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*
|
||||
* Return: A host pointer, or %NULL if the resources needed to
|
||||
* perform the mapping are exhausted (in that case *@plen
|
||||
* is set to zero).
|
||||
*/
|
||||
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
|
||||
dma_addr_t *plen, DMADirection dir)
|
||||
{
|
||||
return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
}
|
||||
|
||||
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
|
||||
DMADirection dir, dma_addr_t access_len)
|
||||
{
|
||||
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
|
||||
}
|
||||
|
||||
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
|
||||
int alloc_hint)
|
||||
{
|
||||
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
|
||||
}
|
||||
|
||||
extern const VMStateDescription vmstate_pci_device;
|
||||
|
||||
#define VMSTATE_PCI_DEVICE(_field, _state) { \
|
||||
.name = (stringify(_field)), \
|
||||
.size = sizeof(PCIDevice), \
|
||||
.vmsd = &vmstate_pci_device, \
|
||||
.flags = VMS_STRUCT, \
|
||||
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
|
||||
}
|
||||
|
||||
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
||||
.name = (stringify(_field)), \
|
||||
.size = sizeof(PCIDevice), \
|
||||
.vmsd = &vmstate_pci_device, \
|
||||
.flags = VMS_STRUCT | VMS_POINTER, \
|
||||
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
|
||||
}
|
||||
|
||||
MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
|
||||
void pci_set_power(PCIDevice *pci_dev, bool state);
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#ifndef QEMU_PCI_BRIDGE_H
|
||||
#define QEMU_PCI_BRIDGE_H
|
||||
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "hw/pci/pci_bus.h"
|
||||
#include "hw/cxl/cxl.h"
|
||||
#include "qom/object.h"
|
||||
|
|
|
|||
350
include/hw/pci/pci_device.h
Normal file
350
include/hw/pci/pci_device.h
Normal file
|
|
@ -0,0 +1,350 @@
|
|||
#ifndef QEMU_PCI_DEVICE_H
|
||||
#define QEMU_PCI_DEVICE_H
|
||||
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pcie.h"
|
||||
|
||||
#define TYPE_PCI_DEVICE "pci-device"
|
||||
typedef struct PCIDeviceClass PCIDeviceClass;
|
||||
DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
|
||||
PCI_DEVICE, TYPE_PCI_DEVICE)
|
||||
|
||||
/*
|
||||
* Implemented by devices that can be plugged on CXL buses. In the spec, this is
|
||||
* actually a "CXL Component, but we name it device to match the PCI naming.
|
||||
*/
|
||||
#define INTERFACE_CXL_DEVICE "cxl-device"
|
||||
|
||||
/* Implemented by devices that can be plugged on PCI Express buses */
|
||||
#define INTERFACE_PCIE_DEVICE "pci-express-device"
|
||||
|
||||
/* Implemented by devices that can be plugged on Conventional PCI buses */
|
||||
#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
|
||||
|
||||
struct PCIDeviceClass {
|
||||
DeviceClass parent_class;
|
||||
|
||||
void (*realize)(PCIDevice *dev, Error **errp);
|
||||
PCIUnregisterFunc *exit;
|
||||
PCIConfigReadFunc *config_read;
|
||||
PCIConfigWriteFunc *config_write;
|
||||
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint8_t revision;
|
||||
uint16_t class_id;
|
||||
uint16_t subsystem_vendor_id; /* only for header type = 0 */
|
||||
uint16_t subsystem_id; /* only for header type = 0 */
|
||||
|
||||
const char *romfile; /* rom bar */
|
||||
};
|
||||
|
||||
enum PCIReqIDType {
|
||||
PCI_REQ_ID_INVALID = 0,
|
||||
PCI_REQ_ID_BDF,
|
||||
PCI_REQ_ID_SECONDARY_BUS,
|
||||
PCI_REQ_ID_MAX,
|
||||
};
|
||||
typedef enum PCIReqIDType PCIReqIDType;
|
||||
|
||||
struct PCIReqIDCache {
|
||||
PCIDevice *dev;
|
||||
PCIReqIDType type;
|
||||
};
|
||||
typedef struct PCIReqIDCache PCIReqIDCache;
|
||||
|
||||
struct PCIDevice {
|
||||
DeviceState qdev;
|
||||
bool partially_hotplugged;
|
||||
bool has_power;
|
||||
|
||||
/* PCI config space */
|
||||
uint8_t *config;
|
||||
|
||||
/*
|
||||
* Used to enable config checks on load. Note that writable bits are
|
||||
* never checked even if set in cmask.
|
||||
*/
|
||||
uint8_t *cmask;
|
||||
|
||||
/* Used to implement R/W bytes */
|
||||
uint8_t *wmask;
|
||||
|
||||
/* Used to implement RW1C(Write 1 to Clear) bytes */
|
||||
uint8_t *w1cmask;
|
||||
|
||||
/* Used to allocate config space for capabilities. */
|
||||
uint8_t *used;
|
||||
|
||||
/* the following fields are read only */
|
||||
int32_t devfn;
|
||||
/*
|
||||
* Cached device to fetch requester ID from, to avoid the PCI tree
|
||||
* walking every time we invoke PCI request (e.g., MSI). For
|
||||
* conventional PCI root complex, this field is meaningless.
|
||||
*/
|
||||
PCIReqIDCache requester_id_cache;
|
||||
char name[64];
|
||||
PCIIORegion io_regions[PCI_NUM_REGIONS];
|
||||
AddressSpace bus_master_as;
|
||||
MemoryRegion bus_master_container_region;
|
||||
MemoryRegion bus_master_enable_region;
|
||||
|
||||
/* do not access the following fields */
|
||||
PCIConfigReadFunc *config_read;
|
||||
PCIConfigWriteFunc *config_write;
|
||||
|
||||
/* Legacy PCI VGA regions */
|
||||
MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
|
||||
bool has_vga;
|
||||
|
||||
/* Current IRQ levels. Used internally by the generic PCI code. */
|
||||
uint8_t irq_state;
|
||||
|
||||
/* Capability bits */
|
||||
uint32_t cap_present;
|
||||
|
||||
/* Offset of MSI-X capability in config space */
|
||||
uint8_t msix_cap;
|
||||
|
||||
/* MSI-X entries */
|
||||
int msix_entries_nr;
|
||||
|
||||
/* Space to store MSIX table & pending bit array */
|
||||
uint8_t *msix_table;
|
||||
uint8_t *msix_pba;
|
||||
|
||||
/* May be used by INTx or MSI during interrupt notification */
|
||||
void *irq_opaque;
|
||||
|
||||
MSITriggerFunc *msi_trigger;
|
||||
MSIPrepareMessageFunc *msi_prepare_message;
|
||||
MSIxPrepareMessageFunc *msix_prepare_message;
|
||||
|
||||
/* MemoryRegion container for msix exclusive BAR setup */
|
||||
MemoryRegion msix_exclusive_bar;
|
||||
/* Memory Regions for MSIX table and pending bit entries. */
|
||||
MemoryRegion msix_table_mmio;
|
||||
MemoryRegion msix_pba_mmio;
|
||||
/* Reference-count for entries actually in use by driver. */
|
||||
unsigned *msix_entry_used;
|
||||
/* MSIX function mask set or MSIX disabled */
|
||||
bool msix_function_masked;
|
||||
/* Version id needed for VMState */
|
||||
int32_t version_id;
|
||||
|
||||
/* Offset of MSI capability in config space */
|
||||
uint8_t msi_cap;
|
||||
|
||||
/* PCI Express */
|
||||
PCIExpressDevice exp;
|
||||
|
||||
/* SHPC */
|
||||
SHPCDevice *shpc;
|
||||
|
||||
/* Location of option rom */
|
||||
char *romfile;
|
||||
uint32_t romsize;
|
||||
bool has_rom;
|
||||
MemoryRegion rom;
|
||||
uint32_t rom_bar;
|
||||
|
||||
/* INTx routing notifier */
|
||||
PCIINTxRoutingNotifier intx_routing_notifier;
|
||||
|
||||
/* MSI-X notifiers */
|
||||
MSIVectorUseNotifier msix_vector_use_notifier;
|
||||
MSIVectorReleaseNotifier msix_vector_release_notifier;
|
||||
MSIVectorPollNotifier msix_vector_poll_notifier;
|
||||
|
||||
/* ID of standby device in net_failover pair */
|
||||
char *failover_pair_id;
|
||||
uint32_t acpi_index;
|
||||
};
|
||||
|
||||
static inline int pci_intx(PCIDevice *pci_dev)
|
||||
{
|
||||
return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
|
||||
}
|
||||
|
||||
static inline int pci_is_cxl(const PCIDevice *d)
|
||||
{
|
||||
return d->cap_present & QEMU_PCIE_CAP_CXL;
|
||||
}
|
||||
|
||||
static inline int pci_is_express(const PCIDevice *d)
|
||||
{
|
||||
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
||||
}
|
||||
|
||||
static inline int pci_is_express_downstream_port(const PCIDevice *d)
|
||||
{
|
||||
uint8_t type;
|
||||
|
||||
if (!pci_is_express(d) || !d->exp.exp_cap) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
type = pcie_cap_get_type(d);
|
||||
|
||||
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
|
||||
}
|
||||
|
||||
static inline int pci_is_vf(const PCIDevice *d)
|
||||
{
|
||||
return d->exp.sriov_vf.pf != NULL;
|
||||
}
|
||||
|
||||
static inline uint32_t pci_config_size(const PCIDevice *d)
|
||||
{
|
||||
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
||||
}
|
||||
|
||||
static inline uint16_t pci_get_bdf(PCIDevice *dev)
|
||||
{
|
||||
return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
|
||||
}
|
||||
|
||||
uint16_t pci_requester_id(PCIDevice *dev);
|
||||
|
||||
/* DMA access functions */
|
||||
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
|
||||
{
|
||||
return &dev->bus_master_as;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_dma_rw: Read from or write to an address space from PCI device.
|
||||
*
|
||||
* Return a MemTxResult indicating whether the operation succeeded
|
||||
* or failed (eg unassigned memory, device rejected the transaction,
|
||||
* IOMMU fault).
|
||||
*
|
||||
* @dev: #PCIDevice doing the memory access
|
||||
* @addr: address within the #PCIDevice address space
|
||||
* @buf: buffer with the data transferred
|
||||
* @len: the number of bytes to read or write
|
||||
* @dir: indicates the transfer direction
|
||||
*/
|
||||
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
|
||||
void *buf, dma_addr_t len,
|
||||
DMADirection dir, MemTxAttrs attrs)
|
||||
{
|
||||
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
|
||||
dir, attrs);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_dma_read: Read from an address space from PCI device.
|
||||
*
|
||||
* Return a MemTxResult indicating whether the operation succeeded
|
||||
* or failed (eg unassigned memory, device rejected the transaction,
|
||||
* IOMMU fault). Called within RCU critical section.
|
||||
*
|
||||
* @dev: #PCIDevice doing the memory access
|
||||
* @addr: address within the #PCIDevice address space
|
||||
* @buf: buffer with the data transferred
|
||||
* @len: length of the data transferred
|
||||
*/
|
||||
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
|
||||
void *buf, dma_addr_t len)
|
||||
{
|
||||
return pci_dma_rw(dev, addr, buf, len,
|
||||
DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_dma_write: Write to address space from PCI device.
|
||||
*
|
||||
* Return a MemTxResult indicating whether the operation succeeded
|
||||
* or failed (eg unassigned memory, device rejected the transaction,
|
||||
* IOMMU fault).
|
||||
*
|
||||
* @dev: #PCIDevice doing the memory access
|
||||
* @addr: address within the #PCIDevice address space
|
||||
* @buf: buffer with the data transferred
|
||||
* @len: the number of bytes to write
|
||||
*/
|
||||
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
|
||||
const void *buf, dma_addr_t len)
|
||||
{
|
||||
return pci_dma_rw(dev, addr, (void *) buf, len,
|
||||
DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
|
||||
}
|
||||
|
||||
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
|
||||
static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
|
||||
dma_addr_t addr, \
|
||||
uint##_bits##_t *val, \
|
||||
MemTxAttrs attrs) \
|
||||
{ \
|
||||
return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
|
||||
} \
|
||||
static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
|
||||
dma_addr_t addr, \
|
||||
uint##_bits##_t val, \
|
||||
MemTxAttrs attrs) \
|
||||
{ \
|
||||
return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
|
||||
}
|
||||
|
||||
PCI_DMA_DEFINE_LDST(ub, b, 8);
|
||||
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
|
||||
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
|
||||
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
|
||||
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
|
||||
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
|
||||
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
|
||||
|
||||
#undef PCI_DMA_DEFINE_LDST
|
||||
|
||||
/**
|
||||
* pci_dma_map: Map device PCI address space range into host virtual address
|
||||
* @dev: #PCIDevice to be accessed
|
||||
* @addr: address within that device's address space
|
||||
* @plen: pointer to length of buffer; updated on return to indicate
|
||||
* if only a subset of the requested range has been mapped
|
||||
* @dir: indicates the transfer direction
|
||||
*
|
||||
* Return: A host pointer, or %NULL if the resources needed to
|
||||
* perform the mapping are exhausted (in that case *@plen
|
||||
* is set to zero).
|
||||
*/
|
||||
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
|
||||
dma_addr_t *plen, DMADirection dir)
|
||||
{
|
||||
return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
}
|
||||
|
||||
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
|
||||
DMADirection dir, dma_addr_t access_len)
|
||||
{
|
||||
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
|
||||
}
|
||||
|
||||
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
|
||||
int alloc_hint)
|
||||
{
|
||||
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
|
||||
}
|
||||
|
||||
extern const VMStateDescription vmstate_pci_device;
|
||||
|
||||
#define VMSTATE_PCI_DEVICE(_field, _state) { \
|
||||
.name = (stringify(_field)), \
|
||||
.size = sizeof(PCIDevice), \
|
||||
.vmsd = &vmstate_pci_device, \
|
||||
.flags = VMS_STRUCT, \
|
||||
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
|
||||
}
|
||||
|
||||
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
||||
.name = (stringify(_field)), \
|
||||
.size = sizeof(PCIDevice), \
|
||||
.vmsd = &vmstate_pci_device, \
|
||||
.flags = VMS_STRUCT | VMS_POINTER, \
|
||||
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include "hw/pci/pci_bridge.h"
|
||||
#include "hw/pci/pci_bus.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_PCIE_PORT "pcie-port"
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
#include "exec/memory.h"
|
||||
#include "hw/hotplug.h"
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "migration/vmstate.h"
|
||||
|
||||
struct SHPCDevice {
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#ifndef REMOTE_IOHUB_H
|
||||
#define REMOTE_IOHUB_H
|
||||
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "qemu/event_notifier.h"
|
||||
#include "qemu/thread-posix.h"
|
||||
#include "hw/remote/mpqemu-link.h"
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#ifndef PROXY_H
|
||||
#define PROXY_H
|
||||
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "io/channel.h"
|
||||
#include "hw/remote/proxy-memory-listener.h"
|
||||
#include "qemu/event_notifier.h"
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#ifndef SDHCI_H
|
||||
#define SDHCI_H
|
||||
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/sd/sd.h"
|
||||
#include "qom/object.h"
|
||||
|
|
|
|||
|
|
@ -12,8 +12,7 @@
|
|||
#ifndef HW_SOUTHBRIDGE_PIIX_H
|
||||
#define HW_SOUTHBRIDGE_PIIX_H
|
||||
|
||||
#include "hw/pci/pci.h"
|
||||
#include "qom/object.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
|
||||
/* PIRQRC[A:D]: PIRQx Route Control Registers */
|
||||
#define PIIX_PIRQCA 0x60
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#include "hw/xen/interface/io/xenbus.h"
|
||||
|
||||
#include "hw/xen/xen.h"
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci/pci_device.h"
|
||||
#include "hw/xen/trace.h"
|
||||
|
||||
extern xc_interface *xen_xc;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue