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target/ppc: Extract post_load_update_msr

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Extract post_load_update_msr to share between cpu_load_old
and cpu_post_load in updating the msr.

Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-2-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2021-03-23 12:43:31 -06:00 • committed by David Gibson
parent e81f17a3f6
commit edece45d4a
1 changed files with 14 additions and 16 deletions
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30
target/ppc/machine.c
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@ -10,6 +10,18 @@
#include "kvm_ppc.h" #include "kvm_ppc.h"
#include "exec/helper-proto.h" #include "exec/helper-proto.h"
static void post_load_update_msr(CPUPPCState *env)
{
target_ulong msr = env->msr;
/*
* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
* before restoring. Note that this recomputes hflags and mem_idx.
*/
env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
ppc_store_msr(env, msr);
}
static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{ {
PowerPCCPU *cpu = opaque; PowerPCCPU *cpu = opaque;
@ -21,7 +33,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
int32_t slb_nr; int32_t slb_nr;
#endif #endif
target_ulong xer; target_ulong xer;
target_ulong msr;
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
qemu_get_betls(f, &env->gpr[i]); qemu_get_betls(f, &env->gpr[i]);
@ -117,13 +128,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused mmu_idx */
qemu_get_sbe32(f); /* Discard unused power_mode */ qemu_get_sbe32(f); /* Discard unused power_mode */
/* post_load_update_msr(env);
* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
* before restoring. Note that this recomputes hflags and mem_idx.
*/
msr = env->msr;
env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
ppc_store_msr(env, msr);
return 0; return 0;
} }
@ -343,7 +348,6 @@ static int cpu_post_load(void *opaque, int version_id)
PowerPCCPU *cpu = opaque; PowerPCCPU *cpu = opaque;
CPUPPCState *env = &cpu->env; CPUPPCState *env = &cpu->env;
int i; int i;
target_ulong msr;
/* /*
* If we're operating in compat mode, we should be ok as long as * If we're operating in compat mode, we should be ok as long as
@ -417,13 +421,7 @@ static int cpu_post_load(void *opaque, int version_id)
ppc_store_sdr1(env, env->spr[SPR_SDR1]); ppc_store_sdr1(env, env->spr[SPR_SDR1]);
} }
/* post_load_update_msr(env);
* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
* before restoring. Note that this recomputes hflags and mem_idx.
*/
msr = env->msr;
env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
ppc_store_msr(env, msr);
return 0; return 0;
} }