hw/misc: Allwinner A10 DRAM Controller Emulation

During SPL boot several DRAM Controller registers are used. Most
important registers are those related to DRAM initialization and
calibration, where SPL initiates process and waits until certain bit is
set/cleared.

This patch adds these registers, initializes reset values from user's
guide and updates state of registers as SPL expects it.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Strahinja Jankovic 2022-12-26 23:02:58 +01:00 committed by Peter Maydell
parent 423ec28bb8
commit edd3a59d5b
7 changed files with 261 additions and 0 deletions

View file

@ -324,6 +324,7 @@ config ALLWINNER_A10
select ALLWINNER_A10_PIT
select ALLWINNER_A10_PIC
select ALLWINNER_A10_CCM
select ALLWINNER_A10_DRAMC
select ALLWINNER_EMAC
select SERIAL
select UNIMP