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hw/misc: Allwinner A10 DRAM Controller Emulation
During SPL boot several DRAM Controller registers are used. Most important registers are those related to DRAM initialization and calibration, where SPL initiates process and waits until certain bit is set/cleared. This patch adds these registers, initializes reset values from user's guide and updates state of registers as SPL expects it. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -324,6 +324,7 @@ config ALLWINNER_A10
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select ALLWINNER_A10_PIT
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select ALLWINNER_A10_PIC
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select ALLWINNER_A10_CCM
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select ALLWINNER_A10_DRAMC
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select ALLWINNER_EMAC
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select SERIAL
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select UNIMP
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