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i386: move TCG cpu class initialization to tcg/
to do this, we need to take code out of cpu.c and helper.c, and also move some prototypes from cpu.h, for code that is needed in tcg/xxx_helper.c, and which in turn is part of the callbacks registered by the class initialization. Therefore, do some shuffling of the parts of cpu.h that are only relevant for tcg/, and put them in tcg/helper-tcg.h For FT0 and similar macros, put them in tcg/fpu-helper.c since they are used only there. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-8-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Claudio Fontana
Eduardo Habkost
parent
40399ecb69
commit
ed69e8314d
19 changed files with 238 additions and 148 deletions
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@ -31,9 +31,6 @@
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#define KVM_HAVE_MCE_INJECTION 1
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/* Maximum instruction code size */
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#define TARGET_MAX_INSN_SIZE 16
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/* support for self modifying code even if the modified instruction is
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close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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@ -1775,12 +1772,6 @@ struct X86CPU {
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extern VMStateDescription vmstate_x86_cpu;
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#endif
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/**
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* x86_cpu_do_interrupt:
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* @cpu: vCPU the interrupt is to be handled by.
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*/
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void x86_cpu_do_interrupt(CPUState *cpu);
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bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
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int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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@ -1803,9 +1794,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void x86_cpu_exec_enter(CPUState *cpu);
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void x86_cpu_exec_exit(CPUState *cpu);
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void x86_cpu_list(void);
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int cpu_x86_support_mca_broadcast(CPUX86State *env);
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@ -1930,9 +1918,6 @@ void host_cpuid(uint32_t function, uint32_t count,
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void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
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/* helper.c */
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bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
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#ifndef CONFIG_USER_ONLY
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@ -1957,8 +1942,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
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void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
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#endif
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void breakpoint_handler(CPUState *cs);
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/* will be suppressed */
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
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@ -1968,16 +1951,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
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/* hw/pc.c */
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uint64_t cpu_get_tsc(CPUX86State *env);
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/* XXX: This value should match the one returned by CPUID
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* and in exec.c */
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# if defined(TARGET_X86_64)
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# define TCG_PHYS_ADDR_BITS 40
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# else
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# define TCG_PHYS_ADDR_BITS 36
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# endif
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#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
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#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
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#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_X86_CPU
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@ -2014,25 +1987,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
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#define CC_SRC2 (env->cc_src2)
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#define CC_OP (env->cc_op)
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/* n must be a constant to be efficient */
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static inline target_long lshift(target_long x, int n)
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{
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if (n >= 0) {
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return x << n;
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} else {
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return x >> (-n);
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}
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}
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/* float macros */
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#define FT0 (env->ft0)
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#define ST0 (env->fpregs[env->fpstt].d)
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#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
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#define ST1 ST(1)
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/* translate.c */
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void tcg_x86_init(void);
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typedef CPUX86State CPUArchState;
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typedef X86CPU ArchCPU;
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@ -2062,19 +2016,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
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uint64_t status, uint64_t mcg_status, uint64_t addr,
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uint64_t misc, int flags);
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/* excp_helper.c */
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void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
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void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
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uintptr_t retaddr);
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void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
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int error_code);
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void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
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int error_code, uintptr_t retaddr);
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void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
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int error_code, int next_eip_addend);
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/* cc_helper.c */
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extern const uint8_t parity_table[256];
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uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
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static inline uint32_t cpu_compute_eflags(CPUX86State *env)
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@ -2086,18 +2027,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env)
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return eflags;
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}
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/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
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* after generating a call to a helper that uses this.
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*/
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static inline void cpu_load_eflags(CPUX86State *env, int eflags,
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int update_mask)
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{
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CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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CC_OP = CC_OP_EFLAGS;
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env->df = 1 - (2 * ((eflags >> 10) & 1));
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env->eflags = (env->eflags & ~update_mask) |
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(eflags & update_mask) | 0x2;
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}
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/* load efer and update the corresponding hflags. XXX: do consistency
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checks with cpuid bits? */
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@ -2186,16 +2115,6 @@ void helper_lock_init(void);
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/* svm_helper.c */
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void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
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uint64_t param, uintptr_t retaddr);
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void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
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uint64_t exit_info_1, uintptr_t retaddr);
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void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
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/* seg_helper.c */
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void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
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/* smm_helper.c */
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void do_smm_enter(X86CPU *cpu);
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/* apic.c */
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void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
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void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
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@ -2234,11 +2153,6 @@ typedef int X86CPUVersion;
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*/
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void x86_cpu_set_default_version(X86CPUVersion version);
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/* Return name of 32-bit register, from a R_* constant */
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const char *get_register_name_32(unsigned int reg);
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void enable_compat_apic_id_mode(void);
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#define APIC_DEFAULT_ADDRESS 0xfee00000
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#define APIC_SPACE_SIZE 0x100000
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