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virtio,vhost,pci,pc: features, cleanups
SRAT tables for DIMM devices new virtio net flags for speed/duplex post-copy migration support in vhost cleanups in pci Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJasR1rAAoJECgfDbjSjVRpOocH/R9A3g/TkpGjmLzJBrrX1NGO I/iq0ttHjqg4OBIChA4BHHjXwYUMs7XQn26B3efrk1otLAJhuqntZIIo3uU0WraA 5J+4DT46ogs5rZWNzDCZ0zAkSaATDA6h9Nfh7TvPc9Q2WpcIT0cTa/jOtrxRc9Vq 32hbUKtJSpNxRjwbZvk6YV21HtWo3Tktdaj9IeTQTN0/gfMyOMdgxta3+bymicbJ FuF9ybHcpXvrEctHhXHIL4/YVGEH/4shagZ4JVzv1dVdLeHLZtPomdf7+oc0+07m Qs+yV0HeRS5Zxt7w5blGLC4zDXczT/bUx8oln0Tz5MV7RR/+C2HwMOHC69gfpSc= =vomK -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging virtio,vhost,pci,pc: features, cleanups SRAT tables for DIMM devices new virtio net flags for speed/duplex post-copy migration support in vhost cleanups in pci Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 20 Mar 2018 14:40:43 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (51 commits) postcopy shared docs libvhost-user: Claim support for postcopy postcopy: Allow shared memory vhost: Huge page align and merge vhost+postcopy: Wire up POSTCOPY_END notify vhost-user: Add VHOST_USER_POSTCOPY_END message libvhost-user: mprotect & madvises for postcopy vhost+postcopy: Call wakeups vhost+postcopy: Add vhost waker postcopy: postcopy_notify_shared_wake postcopy: helper for waking shared vhost+postcopy: Resolve client address postcopy-ram: add a stub for postcopy_request_shared_page vhost+postcopy: Helper to send requests to source for shared pages vhost+postcopy: Stash RAMBlock and offset vhost+postcopy: Send address back to qemu libvhost-user+postcopy: Register new regions with the ufd migration/ram: ramblock_recv_bitmap_test_byte_offset postcopy+vhost-user: Split set_mem_table for postcopy vhost+postcopy: Transmit 'listen' to slave ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # scripts/update-linux-headers.sh
This commit is contained in:
Peter Maydell
commit
ed627b2ad3
55 changed files with 3767 additions and 536 deletions
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@ -40,18 +40,6 @@ enum {
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ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
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};
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/*
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* ACPI 2.0 Generic Address Space definition.
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*/
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struct Acpi20GenericAddress {
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uint8_t address_space_id;
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uint8_t register_bit_width;
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uint8_t register_bit_offset;
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uint8_t reserved;
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uint64_t address;
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} QEMU_PACKED;
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typedef struct Acpi20GenericAddress Acpi20GenericAddress;
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struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
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uint64_t signature; /* ACPI signature, contains "RSD PTR " */
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uint8_t checksum; /* To make sum of struct == 0 */
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@ -87,104 +75,44 @@ struct AcpiTableHeader {
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} QEMU_PACKED;
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typedef struct AcpiTableHeader AcpiTableHeader;
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/*
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* ACPI Fixed ACPI Description Table (FADT)
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*/
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#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
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uint32_t firmware_ctrl; /* Physical address of FACS */ \
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uint32_t dsdt; /* Physical address of DSDT */ \
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uint8_t model; /* System Interrupt Model */ \
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uint8_t reserved1; /* Reserved */ \
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uint16_t sci_int; /* System vector of SCI interrupt */ \
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uint32_t smi_cmd; /* Port address of SMI command port */ \
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uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
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uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
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/* Value to write to SMI CMD to enter S4BIOS state */ \
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uint8_t S4bios_req; \
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uint8_t reserved2; /* Reserved - must be zero */ \
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/* Port address of Power Mgt 1a acpi_event Reg Blk */ \
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uint32_t pm1a_evt_blk; \
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/* Port address of Power Mgt 1b acpi_event Reg Blk */ \
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uint32_t pm1b_evt_blk; \
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uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
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uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
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uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
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uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
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/* Port addr of General Purpose acpi_event 0 Reg Blk */ \
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uint32_t gpe0_blk; \
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/* Port addr of General Purpose acpi_event 1 Reg Blk */ \
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uint32_t gpe1_blk; \
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uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
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uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
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uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
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uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
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uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
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uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
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uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
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uint8_t reserved3; /* Reserved */ \
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uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
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uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
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uint16_t flush_size; /* Size of area read to flush caches */ \
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uint16_t flush_stride; /* Stride used in flushing caches */ \
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uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
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uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
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uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
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uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
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uint8_t century; /* Index to century in RTC CMOS RAM */ \
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/* IA-PC Boot Architecture Flags (see below for individual flags) */ \
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uint16_t boot_flags; \
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uint8_t reserved; /* Reserved, must be zero */ \
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/* Miscellaneous flag bits (see below for individual flags) */ \
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uint32_t flags; \
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/* 64-bit address of the Reset register */ \
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struct AcpiGenericAddress reset_register; \
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/* Value to write to the reset_register port to reset the system */ \
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uint8_t reset_value; \
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/* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */ \
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uint16_t arm_boot_flags; \
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uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ \
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uint64_t x_facs; /* 64-bit physical address of FACS */ \
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uint64_t x_dsdt; /* 64-bit physical address of DSDT */ \
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/* 64-bit Extended Power Mgt 1a Event Reg Blk address */ \
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struct AcpiGenericAddress xpm1a_event_block; \
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/* 64-bit Extended Power Mgt 1b Event Reg Blk address */ \
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struct AcpiGenericAddress xpm1b_event_block; \
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/* 64-bit Extended Power Mgt 1a Control Reg Blk address */ \
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struct AcpiGenericAddress xpm1a_control_block; \
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/* 64-bit Extended Power Mgt 1b Control Reg Blk address */ \
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struct AcpiGenericAddress xpm1b_control_block; \
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/* 64-bit Extended Power Mgt 2 Control Reg Blk address */ \
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struct AcpiGenericAddress xpm2_control_block; \
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/* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ \
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struct AcpiGenericAddress xpm_timer_block; \
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/* 64-bit Extended General Purpose Event 0 Reg Blk address */ \
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struct AcpiGenericAddress xgpe0_block; \
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/* 64-bit Extended General Purpose Event 1 Reg Blk address */ \
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struct AcpiGenericAddress xgpe1_block; \
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struct AcpiGenericAddress {
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uint8_t space_id; /* Address space where struct or register exists */
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uint8_t bit_width; /* Size in bits of given register */
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uint8_t bit_offset; /* Bit offset within the register */
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uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
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uint8_t access_width; /* ACPI 3.0: Minimum Access size (ACPI 3.0),
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ACPI 2.0: Reserved, Table 5-1 */
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uint64_t address; /* 64-bit address of struct or register */
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} QEMU_PACKED;
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struct AcpiFadtDescriptorRev3 {
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ACPI_FADT_COMMON_DEF
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} QEMU_PACKED;
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typedef struct AcpiFadtDescriptorRev3 AcpiFadtDescriptorRev3;
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typedef struct AcpiFadtData {
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struct AcpiGenericAddress pm1a_cnt; /* PM1a_CNT_BLK */
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struct AcpiGenericAddress pm1a_evt; /* PM1a_EVT_BLK */
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struct AcpiGenericAddress pm_tmr; /* PM_TMR_BLK */
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struct AcpiGenericAddress gpe0_blk; /* GPE0_BLK */
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struct AcpiGenericAddress reset_reg; /* RESET_REG */
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uint8_t reset_val; /* RESET_VALUE */
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uint8_t rev; /* Revision */
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uint32_t flags; /* Flags */
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uint32_t smi_cmd; /* SMI_CMD */
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uint16_t sci_int; /* SCI_INT */
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uint8_t int_model; /* INT_MODEL */
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uint8_t acpi_enable_cmd; /* ACPI_ENABLE */
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uint8_t acpi_disable_cmd; /* ACPI_DISABLE */
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uint8_t rtc_century; /* CENTURY */
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uint16_t plvl2_lat; /* P_LVL2_LAT */
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uint16_t plvl3_lat; /* P_LVL3_LAT */
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uint16_t arm_boot_arch; /* ARM_BOOT_ARCH */
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uint8_t minor_ver; /* FADT Minor Version */
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struct AcpiFadtDescriptorRev5_1 {
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ACPI_FADT_COMMON_DEF
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/* 64-bit Sleep Control register (ACPI 5.0) */
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struct AcpiGenericAddress sleep_control;
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/* 64-bit Sleep Status register (ACPI 5.0) */
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struct AcpiGenericAddress sleep_status;
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} QEMU_PACKED;
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typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
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/*
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* respective tables offsets within ACPI_BUILD_TABLE_FILE,
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* NULL if table doesn't exist (in that case field's value
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* won't be patched by linker and will be kept set to 0)
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*/
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unsigned *facs_tbl_offset; /* FACS offset in */
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unsigned *dsdt_tbl_offset;
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unsigned *xdsdt_tbl_offset;
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} AcpiFadtData;
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#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
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#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
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@ -456,7 +384,7 @@ typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
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struct Acpi20Hpet {
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t timer_block_id;
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Acpi20GenericAddress addr;
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struct AcpiGenericAddress addr;
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uint8_t hpet_number;
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uint16_t min_tick;
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uint8_t page_protect;
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@ -77,6 +77,15 @@ typedef enum {
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AML_WRITE_AS_ZEROS = 2,
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} AmlUpdateRule;
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typedef enum {
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AML_AS_SYSTEM_MEMORY = 0X00,
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AML_AS_SYSTEM_IO = 0X01,
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AML_AS_PCI_CONFIG = 0X02,
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AML_AS_EMBEDDED_CTRL = 0X03,
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AML_AS_SMBUS = 0X04,
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AML_AS_FFH = 0X7F,
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} AmlAddressSpace;
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typedef enum {
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AML_SYSTEM_MEMORY = 0X00,
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AML_SYSTEM_IO = 0X01,
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@ -389,8 +398,22 @@ int
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build_append_named_dword(GArray *array, const char *name_format, ...)
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GCC_FMT_ATTR(2, 3);
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void build_append_gas(GArray *table, AmlAddressSpace as,
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uint8_t bit_width, uint8_t bit_offset,
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uint8_t access_width, uint64_t address);
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static inline void
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build_append_gas_from_struct(GArray *table, const struct AcpiGenericAddress *s)
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{
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build_append_gas(table, s->space_id, s->bit_width, s->bit_offset,
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s->access_width, s->address);
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}
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void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
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uint64_t len, int node, MemoryAffinityFlags flags);
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void build_slit(GArray *table_data, BIOSLinker *linker);
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void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
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const char *oem_id, const char *oem_table_id);
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#endif
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@ -5,6 +5,9 @@
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#include "hw/hw.h"
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#include "exec/memory.h"
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#define APM_CNT_IOPORT 0xb2
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#define ACPI_PORT_SMI_CMD APM_CNT_IOPORT
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typedef void (*apm_ctrl_changed_t)(uint32_t val, void *arg);
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typedef struct APMState {
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@ -93,7 +93,7 @@ uint64_t pc_dimm_get_free_addr(uint64_t address_space_start,
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int pc_dimm_get_free_slot(const int *hint, int max_slots, Error **errp);
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int qmp_pc_dimm_device_list(Object *obj, void *opaque);
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MemoryDeviceInfoList *qmp_pc_dimm_device_list(void);
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uint64_t pc_existing_dimms_capacity(Error **errp);
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uint64_t get_plugged_memory_size(void);
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void pc_dimm_memory_plug(DeviceState *dev, MemoryHotplugState *hpms,
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@ -217,7 +217,6 @@ typedef struct PCIDeviceClass {
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DeviceClass parent_class;
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void (*realize)(PCIDevice *dev, Error **errp);
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int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */
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PCIUnregisterFunc *exit;
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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@ -38,6 +38,9 @@ typedef struct virtio_net_conf
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uint16_t rx_queue_size;
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uint16_t tx_queue_size;
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uint16_t mtu;
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int32_t speed;
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char *duplex_str;
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uint8_t duplex;
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} virtio_net_conf;
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/* Maximum packet size we can receive from tap device: header + 64k */
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@ -67,7 +70,7 @@ typedef struct VirtIONet {
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uint32_t has_vnet_hdr;
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size_t host_hdr_len;
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size_t guest_hdr_len;
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uint32_t host_features;
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uint64_t host_features;
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uint8_t has_ufo;
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uint32_t mergeable_rx_bufs;
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uint8_t promisc;
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