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Misc hardware patch queue

Browse source 
HW emulation:
 - PMBus fixes and tests (Titus)
 - IDE fixes and tests (Fiona)
 - New ADM1266 sensor (Titus)
 - Better error propagation in PCI-ISA i82378 (Philippe)
 - Declare SD model QOM types using DEFINE_TYPES macro (Philippe)
 
 Topology:
 - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)
 
 Monitor:
 - Synchronize CPU state in 'info lapic' (Dongli Zhang)
 
 QOM:
 - Have 'cpu-qom.h' target-agnostic (Philippe)
 - Move ArchCPUClass definition to each target's cpu.h (Philippe)
 - Call object_class_is_abstract once in cpu_class_by_name (Philippe)
 
 UI:
 - Use correct key names in titles on MacOS / SDL2 (Adrian)
 
 MIPS:
 - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)
 
 Nios2:
 - Create IRQs *after* vCPU is realized (Philippe)
 
 PPC:
 - Restrict KVM objects to system emulation (Philippe)
 - Move target-specific definitions out of 'cpu-qom.h' (Philippe)
 
 S390X:
 - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)
 
 X86:
 - HVF & KVM cleanups (Philippe)
 
 Various targets:
 - Use env_archcpu() to optimize (Philippe)
 
 Misc:
 - Few global variable shadowing removed (Philippe)
 - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
 - Remove few more 'softmmu' mentions (Philippe)
 - Fix and cleanup in vl.c (Akihiko & Marc-André)
 - Resource leak fix in dump (Zongmin Zhou)
 - MAINTAINERS updates (Thomas, Daniel)
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Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging

Misc hardware patch queue

HW emulation:
- PMBus fixes and tests (Titus)
- IDE fixes and tests (Fiona)
- New ADM1266 sensor (Titus)
- Better error propagation in PCI-ISA i82378 (Philippe)
- Declare SD model QOM types using DEFINE_TYPES macro (Philippe)

Topology:
- Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)

Monitor:
- Synchronize CPU state in 'info lapic' (Dongli Zhang)

QOM:
- Have 'cpu-qom.h' target-agnostic (Philippe)
- Move ArchCPUClass definition to each target's cpu.h (Philippe)
- Call object_class_is_abstract once in cpu_class_by_name (Philippe)

UI:
- Use correct key names in titles on MacOS / SDL2 (Adrian)

MIPS:
- Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)

Nios2:
- Create IRQs *after* vCPU is realized (Philippe)

PPC:
- Restrict KVM objects to system emulation (Philippe)
- Move target-specific definitions out of 'cpu-qom.h' (Philippe)

S390X:
- Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)

X86:
- HVF & KVM cleanups (Philippe)

Various targets:
- Use env_archcpu() to optimize (Philippe)

Misc:
- Few global variable shadowing removed (Philippe)
- Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
- Remove few more 'softmmu' mentions (Philippe)
- Fix and cleanup in vl.c (Akihiko & Marc-André)
- Resource leak fix in dump (Zongmin Zhou)
- MAINTAINERS updates (Thomas, Daniel)

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# gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits)
  dump: Add close fd on error return to avoid resource leak
  ui/sdl2: use correct key names in win title on mac
  MAINTAINERS: Add more guest-agent related files to the corresponding section
  MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section
  MAINTAINERS: update libvirt devel mailing list address
  MAINTAINERS: Add the CAN documentation file to the CAN section
  MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section
  hw/sd: Declare QOM types using DEFINE_TYPES() macro
  hw/i2c: pmbus: reset page register for out of range reads
  hw/i2c: pmbus: immediately clear faults on request
  tests/qtest: add tests for ADM1266
  hw/sensor: add ADM1266 device model
  hw/i2c: pmbus: add VCAP register
  hw/i2c: pmbus: add fan support
  hw/i2c: pmbus: add vout mode bitfields
  hw/i2c: pmbus add support for block receive
  tests/qtest: ahci-test: add test exposing reset issue with pending callback
  hw/ide: reset: cancel async DMA operation before resetting state
  hw/cpu: Update the comments of nr_cores and nr_dies
  system/cpus: Fix CPUState.nr_cores' calculation
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-08 08:32:26 +08:00
commit ed1d873caa
134 changed files with 1722 additions and 1085 deletions
Download patch file Download diff file Expand all files Collapse all files

21
target/alpha/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU Alpha CPU
* QEMU Alpha CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,27 +21,12 @@
#define QEMU_ALPHA_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_ALPHA_CPU "alpha-cpu"
OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
/**
* AlphaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An Alpha CPU model.
*/
struct AlphaCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
#endif

10
target/alpha/cpu.c
View file

@ -126,8 +126,7 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
int i;
oc = object_class_by_name(cpu_model);
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
!object_class_is_abstract(oc)) {
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) {
return oc;
}
@ -142,13 +141,10 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && object_class_is_abstract(oc)) {
oc = NULL;
}
/* TODO: remove match everything nonsense */
/* Default to ev67; no reason not to emulate insns by default. */
if (!oc) {
if (!oc || object_class_is_abstract(oc)) {
/* Default to ev67; no reason not to emulate insns by default. */
oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
}

17
target/alpha/cpu.h
View file

@ -259,9 +259,7 @@ typedef struct CPUArchState {
* An Alpha CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUAlphaState env;
@ -269,6 +267,19 @@ struct ArchCPU {
QEMUTimer *alarm_timer;
};
/**
* AlphaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An Alpha CPU model.
*/
struct AlphaCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_alpha_cpu;
@ -428,8 +439,6 @@ enum {
void alpha_translate_init(void);
#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
void alpha_cpu_list(void);

61
target/arm/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU ARM CPU
* QEMU ARM CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,7 +21,6 @@
#define QEMU_ARM_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_ARM_CPU "arm-cpu"
@ -29,67 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
void arm_cpu_register(const ARMCPUInfo *info);
void aarch64_cpu_register(const ARMCPUInfo *info);
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An ARM CPU model.
*/
struct ARMCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
const ARMCPUInfo *info;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define TYPE_AARCH64_CPU "aarch64-cpu"
typedef struct AArch64CPUClass AArch64CPUClass;
DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU)
struct AArch64CPUClass {
/*< private >*/
ARMCPUClass parent_class;
/*< public >*/
};
void register_cp_regs_for_features(ARMCPU *cpu);
void init_cpreg_list(ARMCPU *cpu);
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
void arm_gt_hvtimer_cb(void *opaque);
#define ARM_AFF0_SHIFT 0
#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
#define ARM_AFF1_SHIFT 8
#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
#define ARM_AFF2_SHIFT 16
#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
#define ARM_AFF3_SHIFT 32
#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
#define ARM64_AFFINITY_MASK \
(ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
#endif

3
target/arm/cpu.c
View file

@ -2401,8 +2401,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
object_class_is_abstract(oc)) {
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU)) {
return NULL;
}
return oc;

49
target/arm/cpu.h
View file

@ -852,9 +852,7 @@ typedef struct {
* An ARM CPU core.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUARMState env;
@ -1118,11 +1116,58 @@ struct ArchCPU {
uint64_t gt_cntfrq_hz;
};
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An ARM CPU model.
*/
struct ARMCPUClass {
CPUClass parent_class;
const ARMCPUInfo *info;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
struct AArch64CPUClass {
ARMCPUClass parent_class;
};
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
void arm_gt_hvtimer_cb(void *opaque);
unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
void arm_cpu_post_init(Object *obj);
#define ARM_AFF0_SHIFT 0
#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
#define ARM_AFF1_SHIFT 8
#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
#define ARM_AFF2_SHIFT 16
#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
#define ARM_AFF3_SHIFT 32
#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
#define ARM64_AFFINITY_MASK \
(ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
#ifndef CONFIG_USER_ONLY

6
target/arm/internals.h
View file

@ -183,6 +183,12 @@ static inline int r14_bank_number(int mode)
return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
}
void arm_cpu_register(const ARMCPUInfo *info);
void aarch64_cpu_register(const ARMCPUInfo *info);
void register_cp_regs_for_features(ARMCPU *cpu);
void init_cpreg_list(ARMCPU *cpu);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);

20
target/avr/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU AVR CPU
* QEMU AVR CPU QOM header (target agnostic)
*
* Copyright (c) 2016-2020 Michael Rolnik
*
@ -22,26 +22,12 @@
#define TARGET_AVR_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_AVR_CPU "avr-cpu"
OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
/**
* AVRCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A AVR CPU model.
*/
struct AVRCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
#endif /* TARGET_AVR_CPU_QOM_H */

3
target/avr/cpu.c
View file

@ -157,8 +157,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
ObjectClass *oc;
oc = object_class_by_name(cpu_model);
if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
object_class_is_abstract(oc)) {
if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL) {
oc = NULL;
}
return oc;

18
target/avr/cpu.h
View file

@ -28,8 +28,6 @@
#error "AVR 8-bit does not support user mode"
#endif
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
#define TCG_GUEST_DEFAULT_MO 0
@ -144,13 +142,25 @@ typedef struct CPUArchState {
* A AVR CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUAVRState env;
};
/**
* AVRCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A AVR CPU model.
*/
struct AVRCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
extern const struct VMStateDescription vms_avr_cpu;
void avr_cpu_do_interrupt(CPUState *cpu);

24
target/cris/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU CRIS CPU
* QEMU CRIS CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,30 +21,12 @@
#define QEMU_CRIS_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_CRIS_CPU "cris-cpu"
OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/**
* CRISCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value.
*
* A CRIS CPU model.
*/
struct CRISCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t vr;
};
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#endif

3
target/cris/cpu.c
View file

@ -95,8 +95,7 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
object_class_is_abstract(oc))) {
if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_CRIS_CPU)) {
oc = NULL;
}
return oc;

20
target/cris/cpu.h
View file

@ -174,13 +174,27 @@ typedef struct CPUArchState {
* A CRIS CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUCRISState env;
};
/**
* CRISCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value.
*
* A CRIS CPU model.
*/
struct CRISCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t vr;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_cris_cpu;
@ -242,8 +256,6 @@ enum {
/* CRIS uses 8k pages. */
#define MMAP_SHIFT TARGET_PAGE_BITS
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
/* MMU modes definitions */

27
target/hexagon/cpu-qom.h Normal file
View file

@ -0,0 +1,27 @@
/*
* QEMU Hexagon CPU QOM header (target agnostic)
*
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef QEMU_HEXAGON_CPU_QOM_H
#define QEMU_HEXAGON_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_HEXAGON_CPU "hexagon-cpu"
#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
#endif

3
target/hexagon/cpu.c
View file

@ -63,8 +63,7 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) ||
object_class_is_abstract(oc)) {
if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU)) {
return NULL;
}
return oc;

20
target/hexagon/cpu.h
View file

@ -20,11 +20,10 @@
#include "fpu/softfloat-types.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
#include "mmvec/mmvec.h"
#include "qom/object.h"
#include "hw/core/cpu.h"
#include "hw/registerfields.h"
#define NUM_PREGS 4
@ -36,18 +35,8 @@
#define PRED_WRITES_MAX 5 /* 4 insns + endloop */
#define VSTORES_MAX 2
#define TYPE_HEXAGON_CPU "hexagon-cpu"
#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
void hexagon_cpu_list(void);
#define cpu_list hexagon_cpu_list
@ -127,20 +116,15 @@ typedef struct CPUArchState {
VTCMStoreLog vtcm_log;
} CPUHexagonState;
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
} HexagonCPUClass;
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUHexagonState env;

20
target/hppa/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU HPPA CPU
* QEMU HPPA CPU QOM header (target agnostic)
*
* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
*
@ -21,28 +21,10 @@
#define QEMU_HPPA_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_HPPA_CPU "hppa-cpu"
#define TYPE_HPPA64_CPU "hppa64-cpu"
OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
/**
* HPPACPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An HPPA CPU model.
*/
struct HPPACPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#endif

16
target/hppa/cpu.h
View file

@ -247,14 +247,26 @@ typedef struct CPUArchState {
* An HPPA CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUHPPAState env;
QEMUTimer *alarm_timer;
};
/**
* HPPACPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An HPPA CPU model.
*/
struct HPPACPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#include "exec/cpu-all.h"
static inline bool hppa_is_pa20(CPUHPPAState *env)

42
target/i386/cpu-qom.h
View file

@ -21,8 +21,6 @@
#define QEMU_I386_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qemu/notify.h"
#include "qom/object.h"
#ifdef TARGET_X86_64
#define TYPE_X86_CPU "x86_64-cpu"
@ -32,43 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
typedef struct X86CPUModel X86CPUModel;
/**
* X86CPUClass:
* @cpu_def: CPU model definition
* @host_cpuid_required: Whether CPU model requires cpuid from host.
* @ordering: Ordering on the "-cpu help" CPU model list.
* @migration_safe: See CpuDefinitionInfo::migration_safe
* @static_model: See CpuDefinitionInfo::static
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An x86 CPU model or family.
*/
struct X86CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
/* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
X86CPUModel *model;
bool host_cpuid_required;
int ordering;
bool migration_safe;
bool static_model;
/* Optional description of CPU model.
* If unavailable, cpu_def->model_id is used */
const char *model_description;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
};
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#endif

9
target/i386/cpu.c
View file

@ -6019,7 +6019,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
X86CPUTopoInfo topo_info;
topo_info.dies_per_pkg = env->nr_dies;
topo_info.cores_per_die = cs->nr_cores;
topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
topo_info.threads_per_core = cs->nr_threads;
/* Calculate & apply limits for different index ranges */
@ -6095,8 +6095,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*/
if (*eax & 31) {
int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
int vcpus_per_socket = env->nr_dies * cs->nr_cores *
cs->nr_threads;
int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
if (cs->nr_cores > 1) {
*eax &= ~0xFC000000;
*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
@ -6273,12 +6272,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 1:
*eax = apicid_die_offset(&topo_info);
*ebx = cs->nr_cores * cs->nr_threads;
*ebx = topo_info.cores_per_die * topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
default:

43
target/i386/cpu.h
View file

@ -1882,6 +1882,7 @@ typedef struct CPUArchState {
TPRAccess tpr_access_type;
/* Number of dies within this CPU package. */
unsigned nr_dies;
} CPUX86State;
@ -1897,9 +1898,7 @@ struct kvm_msrs;
* An x86 CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUX86State env;
VMChangeStateEntry *vmsentry;
@ -2039,6 +2038,44 @@ struct ArchCPU {
bool xen_vapic;
};
typedef struct X86CPUModel X86CPUModel;
/**
* X86CPUClass:
* @cpu_def: CPU model definition
* @host_cpuid_required: Whether CPU model requires cpuid from host.
* @ordering: Ordering on the "-cpu help" CPU model list.
* @migration_safe: See CpuDefinitionInfo::migration_safe
* @static_model: See CpuDefinitionInfo::static
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An x86 CPU model or family.
*/
struct X86CPUClass {
CPUClass parent_class;
/*
* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
X86CPUModel *model;
bool host_cpuid_required;
int ordering;
bool migration_safe;
bool static_model;
/*
* Optional description of CPU model.
* If unavailable, cpu_def->model_id is used.
*/
const char *model_description;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_x86_cpu;
@ -2241,8 +2278,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
#ifdef TARGET_X86_64

4
target/i386/hvf/hvf.c
View file

@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu)
{
load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
simulate_rdmsr(cpu);
simulate_rdmsr(env);
} else {
simulate_wrmsr(cpu);
simulate_wrmsr(env);
}
env->eip += ins_len;
store_regs(cpu);

111
target/i386/hvf/x86_emu.c
View file

@ -45,7 +45,7 @@
#include "vmcs.h"
#include "vmx.h"
void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
void hvf_handle_io(CPUState *cs, uint16_t port, void *data,
int direction, int size, uint32_t count);
#define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
@ -663,35 +663,34 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void simulate_rdmsr(struct CPUState *cpu)
void simulate_rdmsr(CPUX86State *env)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
switch (msr) {
case MSR_IA32_TSC:
val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET);
val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break;
case MSR_IA32_APICBASE:
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
val = cpu_get_apic_base(cpu->apic_state);
break;
case MSR_IA32_UCODE_REV:
val = x86_cpu->ucode_rev;
val = cpu->ucode_rev;
break;
case MSR_EFER:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER);
val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
break;
case MSR_FSBASE:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE);
val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE);
break;
case MSR_GSBASE:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE);
val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE);
break;
case MSR_KERNELGSBASE:
val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE);
val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE);
break;
case MSR_STAR:
abort();
@ -746,7 +745,7 @@ void simulate_rdmsr(struct CPUState *cpu)
val = env->mtrr_deftype;
break;
case MSR_CORE_THREAD_COUNT:
val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
break;
default:
@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu)
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_rdmsr(env_cpu(env));
simulate_rdmsr(env);
env->eip += decode->len;
}
void simulate_wrmsr(struct CPUState *cpu)
void simulate_wrmsr(CPUX86State *env)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@ -776,16 +775,16 @@ void simulate_wrmsr(struct CPUState *cpu)
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
cpu_set_apic_base(cpu->apic_state, data);
break;
case MSR_FSBASE:
wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);
wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
break;
case MSR_GSBASE:
wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data);
wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data);
break;
case MSR_KERNELGSBASE:
wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data);
wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data);
break;
case MSR_STAR:
abort();
@ -797,10 +796,10 @@ void simulate_wrmsr(struct CPUState *cpu)
abort();
break;
case MSR_EFER:
/*printf("new efer %llx\n", EFER(cpu));*/
wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data);
/*printf("new efer %llx\n", EFER(cs));*/
wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data);
if (data & MSR_EFER_NXE) {
hv_vcpu_invalidate_tlb(cpu->accel->fd);
hv_vcpu_invalidate_tlb(cs->accel->fd);
}
break;
case MSR_MTRRphysBase(0):
@ -849,14 +848,14 @@ void simulate_wrmsr(struct CPUState *cpu)
/* Related to support known hypervisor interface */
/* if (g_hypervisor_iface)
g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
g_hypervisor_iface->wrmsr_handler(cs, msr, data);
printf("write msr %llx\n", RCX(cpu));*/
printf("write msr %llx\n", RCX(cs));*/
}
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_wrmsr(env_cpu(env));
simulate_wrmsr(env);
env->eip += decode->len;
}
@ -1418,56 +1417,56 @@ static void init_cmd_handler()
}
}
void load_regs(struct CPUState *cpu)
void load_regs(CPUState *cs)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
int i = 0;
RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX);
RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX);
RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX);
RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX);
RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI);
RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI);
RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP);
RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP);
RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
for (i = 8; i < 16; i++) {
RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i);
RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
}
env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
rflags_to_lflags(env);
env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
env->eip = rreg(cs->accel->fd, HV_X86_RIP);
}
void store_regs(struct CPUState *cpu)
void store_regs(CPUState *cs)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
int i = 0;
wreg(cpu->accel->fd, HV_X86_RAX, RAX(env));
wreg(cpu->accel->fd, HV_X86_RBX, RBX(env));
wreg(cpu->accel->fd, HV_X86_RCX, RCX(env));
wreg(cpu->accel->fd, HV_X86_RDX, RDX(env));
wreg(cpu->accel->fd, HV_X86_RSI, RSI(env));
wreg(cpu->accel->fd, HV_X86_RDI, RDI(env));
wreg(cpu->accel->fd, HV_X86_RBP, RBP(env));
wreg(cpu->accel->fd, HV_X86_RSP, RSP(env));
wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) {
wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i));
wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
}
lflags_to_rflags(env);
wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags);
macvm_set_rip(cpu, env->eip);
wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
macvm_set_rip(cs, env->eip);
}
bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{
/*if (hvf_vcpu_id(cpu))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,
/*if (hvf_vcpu_id(cs))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip,
decode_cmd_to_string(ins->cmd));*/
if (!_cmd_handler[ins->cmd].handler) {

4
target/i386/hvf/x86_emu.h
View file

@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
void simulate_rdmsr(struct CPUState *cpu);
void simulate_wrmsr(struct CPUState *cpu);
void simulate_rdmsr(CPUX86State *env);
void simulate_wrmsr(CPUX86State *env);
target_ulong read_reg(CPUX86State *env, int reg, int size);
void write_reg(CPUX86State *env, int reg, target_ulong val, int size);

1
target/i386/kvm/kvm-cpu.c
View file

@ -37,6 +37,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
* -> cpu_exec_realizefn():
* -> accel_cpu_common_realize()
* kvm_cpu_realizefn() -> host_cpu_realizefn()
* -> cpu_common_realizefn()
* -> check/update ucode_rev, phys_bits, mwait
*/
if (cpu->max_features) {

5
target/i386/monitor.c
View file

@ -28,6 +28,7 @@
#include "monitor/hmp-target.h"
#include "monitor/hmp.h"
#include "qapi/qmp/qdict.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc-target.h"
@ -654,7 +655,11 @@ void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
if (qdict_haskey(qdict, "apic-id")) {
int id = qdict_get_try_int(qdict, "apic-id", 0);
cs = cpu_by_arch_id(id);
if (cs) {
cpu_synchronize_state(cs);
}
} else {
cs = mon_get_cpu(mon);
}

23
target/loongarch/cpu-qom.h Normal file
View file

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU LoongArch CPU QOM header (target agnostic)
*
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
#ifndef LOONGARCH_CPU_QOM_H
#define LOONGARCH_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
LOONGARCH_CPU)
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
#endif

3
target/loongarch/cpu.c
View file

@ -721,8 +721,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
}
}
if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)
&& !object_class_is_abstract(oc)) {
if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)) {
return oc;
}
return NULL;

14
target/loongarch/cpu.h
View file

@ -17,6 +17,7 @@
#include "exec/memory.h"
#endif
#include "cpu-csr.h"
#include "cpu-qom.h"
#define IOCSRF_TEMP 0
#define IOCSRF_NODECNT 1
@ -371,9 +372,7 @@ typedef struct CPUArchState {
* A LoongArch CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPULoongArchState env;
QEMUTimer timer;
@ -383,13 +382,6 @@ struct ArchCPU {
const char *dtb_compatible;
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
LOONGARCH_CPU)
/**
* LoongArchCPUClass:
* @parent_realize: The parent class' realize handler.
@ -398,9 +390,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
* A LoongArch CPU model.
*/
struct LoongArchCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
@ -482,8 +472,6 @@ void loongarch_cpu_list(void);
#include "exec/cpu-all.h"
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
void loongarch_cpu_post_init(Object *obj);

21
target/m68k/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU Motorola 68k CPU
* QEMU Motorola 68k CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,27 +21,12 @@
#define QEMU_M68K_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_M68K_CPU "m68k-cpu"
OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
/*
* M68kCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A Motorola 68k CPU model.
*/
struct M68kCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
#endif

3
target/m68k/cpu.c
View file

@ -111,8 +111,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(M68K_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL ||
object_class_is_abstract(oc))) {
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL) {
return NULL;
}
return oc;

17
target/m68k/cpu.h
View file

@ -164,13 +164,24 @@ typedef struct CPUArchState {
* A Motorola 68k CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUM68KState env;
};
/*
* M68kCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A Motorola 68k CPU model.
*/
struct M68kCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#ifndef CONFIG_USER_ONLY
void m68k_cpu_do_interrupt(CPUState *cpu);
@ -563,8 +574,6 @@ enum {
ACCESS_DATA = 0x20, /* Data load/store access */
};
#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
#define cpu_list m68k_cpu_list

20
target/microblaze/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU MicroBlaze CPU
* QEMU MicroBlaze CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,27 +21,9 @@
#define QEMU_MICROBLAZE_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MicroBlaze CPU model.
*/
struct MicroBlazeCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#endif

15
target/microblaze/cpu.h
View file

@ -343,9 +343,7 @@ typedef struct {
* A MicroBlaze CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUMBState env;
@ -357,6 +355,19 @@ struct ArchCPU {
MicroBlazeCPUConfig cfg;
};
/**
* MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MicroBlaze CPU model.
*/
struct MicroBlazeCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#ifndef CONFIG_USER_ONLY
void mb_cpu_do_interrupt(CPUState *cs);

23
target/mips/cpu-qom.h
View file

@ -21,7 +21,6 @@
#define QEMU_MIPS_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#ifdef TARGET_MIPS64
#define TYPE_MIPS_CPU "mips64-cpu"
@ -31,25 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MIPS CPU model.
*/
struct MIPSCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
bool no_data_aborts;
};
#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
#endif

21
target/mips/cpu.h
View file

@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
* A MIPS CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUMIPSState env;
@ -1219,6 +1217,23 @@ struct ArchCPU {
Clock *count_div; /* Divider for CP0_Count clock */
};
/**
* MIPSCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MIPS CPU model.
*/
struct MIPSCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
bool no_data_aborts;
};
void mips_cpu_list(void);
@ -1303,8 +1318,6 @@ enum {
*/
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
bool cpu_type_supports_cps_smp(const char *cpu_type);

4
target/mips/tcg/msa.decode
View file

@ -31,8 +31,8 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:s16 &msa_bz
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
@elm ...... .......... ws:5 wd:5 ...... &msa_elm
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0

2
target/mips/tcg/tx79.decode
View file

@ -24,7 +24,7 @@
@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
@ldst ...... base:5 rt:5 offset:16 &i
@ldst ...... base:5 rt:5 offset:s16 &i
###########################################################################

18
target/nios2/cpu-qom.h Normal file
View file

@ -0,0 +1,18 @@
/*
* QEMU Nios II CPU QOM header (target agnostic)
*
* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef QEMU_NIOS2_CPU_QOM_H
#define QEMU_NIOS2_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
#endif

16
target/nios2/cpu.c
View file

@ -199,14 +199,6 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
Error *local_err = NULL;
#ifndef CONFIG_USER_ONLY
if (cpu->eic_present) {
qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
} else {
qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
}
#endif
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@ -220,6 +212,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
/* We have reserved storage for cpuid; might as well use it. */
cpu->env.ctrl[CR_CPUID] = cs->cpu_index;
#ifndef CONFIG_USER_ONLY
if (cpu->eic_present) {
qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
} else {
qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
}
#endif
ncc->parent_realize(dev, errp);
}

11
target/nios2/cpu.h
View file

@ -21,20 +21,15 @@
#ifndef NIOS2_CPU_H
#define NIOS2_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "hw/registerfields.h"
#include "qom/object.h"
typedef struct CPUArchState CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:
* @parent_phases: The parent class' reset phase handlers.
@ -42,9 +37,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
* A Nios2 CPU model.
*/
struct Nios2CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
@ -214,9 +207,7 @@ typedef struct {
* A Nios2 CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNios2State env;

21
target/openrisc/cpu-qom.h Normal file
View file

@ -0,0 +1,21 @@
/*
* QEMU OpenRISC CPU QOM header (target agnostic)
*
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef QEMU_OPENRISC_CPU_QOM_H
#define QEMU_OPENRISC_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#endif

3
target/openrisc/cpu.c
View file

@ -164,8 +164,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU)) {
return NULL;
}
return oc;

14
target/openrisc/cpu.h
View file

@ -20,17 +20,12 @@
#ifndef OPENRISC_CPU_H
#define OPENRISC_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TCG_GUEST_DEFAULT_MO (0)
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/**
* OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler.
@ -39,9 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
* A OpenRISC CPU model.
*/
struct OpenRISCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
@ -301,14 +294,11 @@ typedef struct CPUArchState {
* A OpenRISC CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUOpenRISCState env;
};
void cpu_openrisc_list(void);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@ -343,8 +333,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#endif
#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
#include "exec/cpu-all.h"

164
target/ppc/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU PowerPC CPU
* QEMU PowerPC CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,7 +21,6 @@
#define QEMU_PPC_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#ifdef TARGET_PPC64
#define TYPE_POWERPC_CPU "powerpc64-cpu"
@ -33,170 +32,9 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
ObjectClass *ppc_cpu_class_by_name(const char *name);
typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;
/*****************************************************************************/
/* MMU model */
typedef enum powerpc_mmu_t powerpc_mmu_t;
enum powerpc_mmu_t {
POWERPC_MMU_UNKNOWN = 0x00000000,
/* Standard 32 bits PowerPC MMU */
POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x00000002,
/*
* PowerPC 74xx MMU with software TLB (this has been
* disabled, see git history for more information.
* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
*/
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
POWERPC_MMU_BOOKE = 0x00000008,
/* BookE 2.06 MMU model */
POWERPC_MMU_BOOKE206 = 0x00000009,
#define POWERPC_MMU_64 0x00010000
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
{
return mmu_model & POWERPC_MMU_64;
}
/*****************************************************************************/
/* Exception model */
typedef enum powerpc_excp_t powerpc_excp_t;
enum powerpc_excp_t {
POWERPC_EXCP_UNKNOWN = 0,
/* Standard PowerPC exception model */
POWERPC_EXCP_STD,
/* PowerPC 40x exception model */
POWERPC_EXCP_40x,
/* PowerPC 603/604/G2 exception model */
POWERPC_EXCP_6xx,
/* PowerPC 7xx exception model */
POWERPC_EXCP_7xx,
/* PowerPC 74xx exception model */
POWERPC_EXCP_74xx,
/* BookE exception model */
POWERPC_EXCP_BOOKE,
/* PowerPC 970 exception model */
POWERPC_EXCP_970,
/* POWER7 exception model */
POWERPC_EXCP_POWER7,
/* POWER8 exception model */
POWERPC_EXCP_POWER8,
/* POWER9 exception model */
POWERPC_EXCP_POWER9,
/* POWER10 exception model */
POWERPC_EXCP_POWER10,
};
/*****************************************************************************/
/* PM instructions */
typedef enum {
PPC_PM_DOZE,
PPC_PM_NAP,
PPC_PM_SLEEP,
PPC_PM_RVWINKLE,
PPC_PM_STOP,
} powerpc_pm_insn_t;
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t powerpc_input_t;
enum powerpc_input_t {
PPC_FLAGS_INPUT_UNKNOWN = 0,
/* PowerPC 6xx bus */
PPC_FLAGS_INPUT_6xx,
/* BookE bus */
PPC_FLAGS_INPUT_BookE,
/* PowerPC 405 bus */
PPC_FLAGS_INPUT_405,
/* PowerPC 970 bus */
PPC_FLAGS_INPUT_970,
/* PowerPC POWER7 bus */
PPC_FLAGS_INPUT_POWER7,
/* PowerPC POWER9 bus */
PPC_FLAGS_INPUT_POWER9,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
};
typedef struct PPCHash64Options PPCHash64Options;
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A PowerPC CPU model.
*/
struct PowerPCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
void (*parent_parse_features)(const char *type, char *str, Error **errp);
uint32_t pvr;
/*
* If @best is false, match if pcc is in the family of pvr
* Else match only if pcc is the best match for pvr in this family.
*/
bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
uint64_t pcr_mask; /* Available bits in PCR register */
uint64_t pcr_supported; /* Bits for supported PowerISA versions */
uint32_t svr;
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
powerpc_input_t bus_model;
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
#ifndef CONFIG_USER_ONLY
unsigned int gdb_num_sprs;
const char *gdb_spr_xml;
#endif
const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
uint32_t lrg_decr_bits;
int n_host_threads;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
};
#ifndef CONFIG_USER_ONLY
typedef struct PPCTimebase {
uint64_t guest_timebase;

145
target/ppc/cpu.h
View file

@ -27,6 +27,8 @@
#include "qom/object.h"
#include "hw/registerfields.h"
#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
#define TCG_GUEST_DEFAULT_MO 0
#define TARGET_PAGE_BITS_64K 16
@ -190,6 +192,95 @@ enum {
POWERPC_EXCP_TRAP = 0x40,
};
/* Exception model */
typedef enum powerpc_excp_t {
POWERPC_EXCP_UNKNOWN = 0,
/* Standard PowerPC exception model */
POWERPC_EXCP_STD,
/* PowerPC 40x exception model */
POWERPC_EXCP_40x,
/* PowerPC 603/604/G2 exception model */
POWERPC_EXCP_6xx,
/* PowerPC 7xx exception model */
POWERPC_EXCP_7xx,
/* PowerPC 74xx exception model */
POWERPC_EXCP_74xx,
/* BookE exception model */
POWERPC_EXCP_BOOKE,
/* PowerPC 970 exception model */
POWERPC_EXCP_970,
/* POWER7 exception model */
POWERPC_EXCP_POWER7,
/* POWER8 exception model */
POWERPC_EXCP_POWER8,
/* POWER9 exception model */
POWERPC_EXCP_POWER9,
/* POWER10 exception model */
POWERPC_EXCP_POWER10,
} powerpc_excp_t;
/*****************************************************************************/
/* MMU model */
typedef enum powerpc_mmu_t {
POWERPC_MMU_UNKNOWN = 0x00000000,
/* Standard 32 bits PowerPC MMU */
POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x00000002,
/*
* PowerPC 74xx MMU with software TLB (this has been
* disabled, see git history for more information.
* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
*/
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
POWERPC_MMU_BOOKE = 0x00000008,
/* BookE 2.06 MMU model */
POWERPC_MMU_BOOKE206 = 0x00000009,
#define POWERPC_MMU_64 0x00010000
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
} powerpc_mmu_t;
static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
{
return mmu_model & POWERPC_MMU_64;
}
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t {
PPC_FLAGS_INPUT_UNKNOWN = 0,
/* PowerPC 6xx bus */
PPC_FLAGS_INPUT_6xx,
/* BookE bus */
PPC_FLAGS_INPUT_BookE,
/* PowerPC 405 bus */
PPC_FLAGS_INPUT_405,
/* PowerPC 970 bus */
PPC_FLAGS_INPUT_970,
/* PowerPC POWER7 bus */
PPC_FLAGS_INPUT_POWER7,
/* PowerPC POWER9 bus */
PPC_FLAGS_INPUT_POWER9,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
} powerpc_input_t;
#define PPC_INPUT(env) ((env)->bus_model)
/*****************************************************************************/
@ -198,9 +289,14 @@ typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
/* Types used to describe some PowerPC registers etc. */
typedef struct DisasContext DisasContext;
typedef struct ppc_dcr_t ppc_dcr_t;
typedef struct ppc_spr_t ppc_spr_t;
typedef struct ppc_tb_t ppc_tb_t;
typedef union ppc_tlb_t ppc_tlb_t;
typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
typedef struct PPCHash64Options PPCHash64Options;
typedef struct CPUArchState CPUPPCState;
/* SPR access micro-ops generations callbacks */
struct ppc_spr_t {
@ -1313,9 +1409,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
* A PowerPC CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUPPCState env;
@ -1341,7 +1435,54 @@ struct ArchCPU {
int32_t mig_slb_nr;
};
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A PowerPC CPU model.
*/
struct PowerPCCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
void (*parent_parse_features)(const char *type, char *str, Error **errp);
uint32_t pvr;
/*
* If @best is false, match if pcc is in the family of pvr
* Else match only if pcc is the best match for pvr in this family.
*/
bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
uint64_t pcr_mask; /* Available bits in PCR register */
uint64_t pcr_supported; /* Bits for supported PowerISA versions */
uint32_t svr;
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
powerpc_input_t bus_model;
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
#ifndef CONFIG_USER_ONLY
unsigned int gdb_num_sprs;
const char *gdb_spr_xml;
#endif
const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
uint32_t lrg_decr_bits;
int n_host_threads;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
};
ObjectClass *ppc_cpu_class_by_name(const char *name);
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);

2
target/ppc/excp_helper.c
View file

@ -3136,7 +3136,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
{
CPUState *cs = env_cpu(env);
PowerPCCPU *cpu = POWERPC_CPU(cs);
PowerPCCPU *cpu = env_archcpu(env);
CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
int ttir = rb & PPC_BITMASK(57, 63);

9
target/ppc/internal.h
View file

@ -20,6 +20,15 @@
#include "hw/registerfields.h"
/* PM instructions */
typedef enum {
PPC_PM_DOZE,
PPC_PM_NAP,
PPC_PM_SLEEP,
PPC_PM_RVWINKLE,
PPC_PM_STOP,
} powerpc_pm_insn_t;
#define FUNC_MASK(name, ret_type, size, max_val) \
static inline ret_type name(uint##size##_t start, \
uint##size##_t end) \

19
target/ppc/kvm-stub.c
View file

@ -1,19 +0,0 @@
/*
* QEMU KVM PPC specific function stubs
*
* Copyright Freescale Inc. 2013
*
* Author: Alexander Graf <agraf@suse.de>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/ppc/openpic_kvm.h"
int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
{
return -EINVAL;
}

4
target/ppc/kvm.c
View file

@ -268,7 +268,7 @@ static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
"KVM failed to provide the MMU features it supports");
}
struct ppc_radix_page_info *kvm_get_radix_page_info(void)
static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void)
{
KVMState *s = KVM_STATE(current_accel());
struct ppc_radix_page_info *radix_page_info;
@ -2368,7 +2368,7 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
}
#if defined(TARGET_PPC64)
pcc->radix_page_info = kvm_get_radix_page_info();
pcc->radix_page_info = kvmppc_get_radix_page_info();
if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
/*

4
target/ppc/kvm_ppc.h
View file

@ -13,6 +13,10 @@
#include "exec/hwaddr.h"
#include "cpu.h"
#ifdef CONFIG_USER_ONLY
#error Cannot include kvm_ppc.h from user emulation
#endif
#ifdef CONFIG_KVM
uint32_t kvmppc_get_tbfreq(void);

2
target/ppc/meson.build
View file

@ -30,7 +30,6 @@ gen = [
]
ppc_ss.add(when: 'CONFIG_TCG', if_true: gen)
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
ppc_system_ss = ss.source_set()
@ -46,6 +45,7 @@ ppc_system_ss.add(when: 'CONFIG_TCG', if_true: files(
), if_false: files(
'tcg-stub.c',
))
ppc_system_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
ppc_system_ss.add(when: 'TARGET_PPC64', if_true: files(
'compat.c',

26
target/riscv/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU RISC-V CPU QOM header
* QEMU RISC-V CPU QOM header (target agnostic)
*
* Copyright (c) 2023 Ventana Micro Systems Inc.
*
@ -20,14 +20,12 @@
#define RISCV_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
@ -45,28 +43,6 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
typedef struct CPUArchState CPURISCVState;
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
*/
struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#endif /* RISCV_CPU_QOM_H */

3
target/riscv/cpu.c
View file

@ -646,8 +646,7 @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
object_class_is_abstract(oc)) {
if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU)) {
return NULL;
}
return oc;

26
target/riscv/cpu.h
View file

@ -32,6 +32,16 @@
#include "qapi/qapi-types-common.h"
#include "cpu-qom.h"
typedef struct CPUArchState CPURISCVState;
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
#define TCG_GUEST_DEFAULT_MO 0
/*
@ -411,9 +421,7 @@ struct CPUArchState {
* A RISCV CPU.
*/
struct ArchCPU {
/* < private > */
CPUState parent_obj;
/* < public > */
CPURISCVState env;
@ -430,6 +438,20 @@ struct ArchCPU {
GHashTable *pmu_event_ctr_map;
};
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
*/
struct RISCVCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
return (env->misa_ext & ext) != 0;

8
target/riscv/internals.h
View file

@ -87,7 +87,7 @@ enum {
static inline uint64_t nanbox_s(CPURISCVState *env, float32 f)
{
/* the value is sign-extended instead of NaN-boxing for zfinx */
if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
if (env_archcpu(env)->cfg.ext_zfinx) {
return (int32_t)f;
} else {
return f | MAKE_64BIT_MASK(32, 32);
@ -97,7 +97,7 @@ static inline uint64_t nanbox_s(CPURISCVState *env, float32 f)
static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
{
/* Disable NaN-boxing check when enable zfinx */
if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
if (env_archcpu(env)->cfg.ext_zfinx) {
return (uint32_t)f;
}
@ -113,7 +113,7 @@ static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
static inline uint64_t nanbox_h(CPURISCVState *env, float16 f)
{
/* the value is sign-extended instead of NaN-boxing for zfinx */
if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
if (env_archcpu(env)->cfg.ext_zfinx) {
return (int16_t)f;
} else {
return f | MAKE_64BIT_MASK(16, 48);
@ -123,7 +123,7 @@ static inline uint64_t nanbox_h(CPURISCVState *env, float16 f)
static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
{
/* Disable nanbox check when enable zfinx */
if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
if (env_archcpu(env)->cfg.ext_zfinx) {
return (uint16_t)f;
}

20
target/rx/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* RX CPU
* QEMU RX CPU QOM header (target agnostic)
*
* Copyright (c) 2019 Yoshinori Sato
*
@ -20,7 +20,6 @@
#define RX_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_RX_CPU "rx-cpu"
@ -28,20 +27,7 @@
OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
/*
* RXCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RX CPU model.
*/
struct RXCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
#endif

6
target/rx/cpu.c
View file

@ -111,16 +111,12 @@ static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
char *typename;
oc = object_class_by_name(cpu_model);
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
!object_class_is_abstract(oc)) {
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) {
return oc;
}
typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && object_class_is_abstract(oc)) {
oc = NULL;
}
return oc;
}

18
target/rx/cpu.h
View file

@ -107,15 +107,25 @@ typedef struct CPUArchState {
* A RX CPU
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPURXState env;
};
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
/*
* RXCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RX CPU model.
*/
struct RXCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
const char *rx_crname(uint8_t cr);

41
target/s390x/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU S/390 CPU
* QEMU S/390 CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,47 +21,12 @@
#define QEMU_S390_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_S390_CPU "s390x-cpu"
OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;
typedef struct CPUArchState CPUS390XState;
typedef enum cpu_reset_type {
S390_CPU_RESET_NORMAL,
S390_CPU_RESET_INITIAL,
S390_CPU_RESET_CLEAR,
} cpu_reset_type;
/**
* S390CPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @load_normal: Performs a load normal.
* @cpu_reset: Performs a CPU reset.
* @initial_cpu_reset: Performs an initial CPU reset.
*
* An S/390 CPU model.
*/
struct S390CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
const S390CPUDef *cpu_def;
bool kvm_required;
bool is_static;
bool is_migration_safe;
const char *desc;
DeviceRealize parent_realize;
DeviceReset parent_reset;
void (*load_normal)(CPUState *cpu);
void (*reset)(CPUState *cpu, cpu_reset_type type);
};
#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
#endif

45
target/s390x/cpu.h
View file

@ -29,7 +29,6 @@
#include "cpu_models.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#include "tcg/tcg_s390x.h"
#include "qapi/qapi-types-machine-common.h"
#define ELF_MACHINE_UNAME "S390X"
@ -56,7 +55,7 @@ typedef struct PSW {
uint64_t addr;
} PSW;
struct CPUArchState {
typedef struct CPUArchState {
uint64_t regs[16]; /* GP registers */
/*
* The floating point registers are part of the vector registers.
@ -158,7 +157,7 @@ struct CPUArchState {
/* currently processed sigp order */
uint8_t sigp_order;
};
} CPUS390XState;
static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
{
@ -172,9 +171,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
* An S/390 CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUS390XState env;
S390CPUModel *model;
@ -183,6 +180,36 @@ struct ArchCPU {
uint32_t irqstate_saved_size;
};
typedef enum cpu_reset_type {
S390_CPU_RESET_NORMAL,
S390_CPU_RESET_INITIAL,
S390_CPU_RESET_CLEAR,
} cpu_reset_type;
/**
* S390CPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @load_normal: Performs a load normal.
* @cpu_reset: Performs a CPU reset.
* @initial_cpu_reset: Performs an initial CPU reset.
*
* An S/390 CPU model.
*/
struct S390CPUClass {
CPUClass parent_class;
const S390CPUDef *cpu_def;
bool kvm_required;
bool is_static;
bool is_migration_safe;
const char *desc;
DeviceRealize parent_realize;
DeviceReset parent_reset;
void (*load_normal)(CPUState *cpu);
void (*reset)(CPUState *cpu, cpu_reset_type type);
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_s390_cpu;
@ -385,6 +412,10 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
#endif
}
#ifdef CONFIG_TCG
#include "tcg/tcg_s390x.h"
static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
@ -407,6 +438,8 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
}
}
#endif /* CONFIG_TCG */
/* PER bits from control register 9 */
#define PER_CR9_EVENT_BRANCH 0x80000000
#define PER_CR9_EVENT_IFETCH 0x40000000
@ -892,8 +925,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
/* helper.c */
#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_S390_CPU
/* interrupt.c */

2
target/s390x/cpu_models.c
View file

@ -757,7 +757,7 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
const S390CPUDef *def = s390_find_cpu_def(type, gen, ec_ga, NULL);
g_assert(def);
g_assert(QTAILQ_EMPTY_RCU(&cpus));
g_assert(QTAILQ_EMPTY_RCU(&cpus_queue));
/* build the CPU model */
s390_qemu_cpu_model.def = def;

8
target/s390x/cpu_models.h
View file

@ -18,7 +18,7 @@
#include "hw/core/cpu.h"
/* static CPU definition */
struct S390CPUDef {
typedef struct S390CPUDef {
const char *name; /* name exposed to the user */
const char *desc; /* description exposed to the user */
uint8_t gen; /* hw generation identification */
@ -38,10 +38,10 @@ struct S390CPUDef {
S390FeatBitmap full_feat;
/* used to init full_feat from generated data */
S390FeatInit full_init;
};
} S390CPUDef;
/* CPU model based on a CPU definition */
struct S390CPUModel {
typedef struct S390CPUModel {
const S390CPUDef *def;
S390FeatBitmap features;
/* values copied from the "host" model, can change during migration */
@ -49,7 +49,7 @@ struct S390CPUModel {
uint32_t cpu_id; /* CPU id */
uint8_t cpu_id_format; /* CPU id format bit */
uint8_t cpu_ver; /* CPU version, usually "ff" for kvm */
};
} S390CPUModel;
/*
* CPU ID

2
target/s390x/diag.c
View file

@ -77,7 +77,7 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
{
bool valid;
CPUState *cs = env_cpu(env);
S390CPU *cpu = S390_CPU(cs);
S390CPU *cpu = env_archcpu(env);
uint64_t addr = env->regs[r1];
uint64_t subcode = env->regs[r3];
IplParameterBlock *iplb;

6
target/s390x/kvm/kvm.c
View file

@ -1174,12 +1174,12 @@ static void kvm_sclp_service_call(S390CPU *cpu, struct kvm_run *run,
break;
case ICPT_PV_INSTR:
g_assert(s390_is_pv());
sclp_service_call_protected(env, sccb, code);
sclp_service_call_protected(cpu, sccb, code);
/* Setting the CC is done by the Ultravisor. */
break;
case ICPT_INSTRUCTION:
g_assert(!s390_is_pv());
r = sclp_service_call(env, sccb, code);
r = sclp_service_call(cpu, sccb, code);
if (r < 0) {
kvm_s390_program_interrupt(cpu, -r);
return;
@ -1358,7 +1358,7 @@ static int kvm_sic_service_call(S390CPU *cpu, struct kvm_run *run)
mode = env->regs[r1] & 0xffff;
isc = (env->regs[r3] >> 27) & 0x7;
r = css_do_sic(env, isc, mode);
r = css_do_sic(cpu, isc, mode);
if (r) {
kvm_s390_program_interrupt(cpu, -r);
}

5
target/s390x/tcg/misc_helper.c
View file

@ -102,7 +102,7 @@ uint64_t HELPER(stck)(CPUS390XState *env)
uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2)
{
qemu_mutex_lock_iothread();
int r = sclp_service_call(env, r1, r2);
int r = sclp_service_call(env_archcpu(env), r1, r2);
qemu_mutex_unlock_iothread();
if (r < 0) {
tcg_s390_program_interrupt(env, -r, GETPC());
@ -761,10 +761,11 @@ void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba,
void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint64_t r3)
{
S390CPU *cpu = env_archcpu(env);
int r;
qemu_mutex_lock_iothread();
r = css_do_sic(env, (r3 >> 27) & 0x7, r1 & 0xffff);
r = css_do_sic(cpu, (r3 >> 27) & 0x7, r1 & 0xffff);
qemu_mutex_unlock_iothread();
/* css_do_sic() may actually return a PGM_xxx value to inject */
if (r) {

28
target/sh4/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU SuperH CPU
* QEMU SuperH CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,7 +21,6 @@
#define QEMU_SUPERH_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_SUPERH_CPU "superh-cpu"
@ -31,28 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
/**
* SuperHCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @pvr: Processor Version Register
* @prr: Processor Revision Register
* @cvr: Cache Version Register
*
* A SuperH CPU model.
*/
struct SuperHCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t pvr;
uint32_t prr;
uint32_t cvr;
};
#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
#endif

3
target/sh4/cpu.c
View file

@ -152,9 +152,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
oc = object_class_by_name(typename);
if (oc != NULL && object_class_is_abstract(oc)) {
oc = NULL;
}
out:
g_free(s);

24
target/sh4/cpu.h
View file

@ -204,13 +204,31 @@ typedef struct CPUArchState {
* A SuperH CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUSH4State env;
};
/**
* SuperHCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @pvr: Processor Version Register
* @prr: Processor Revision Register
* @cvr: Cache Version Register
*
* A SuperH CPU model.
*/
struct SuperHCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t pvr;
uint32_t prr;
uint32_t cvr;
};
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@ -252,8 +270,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
void cpu_load_tlb(CPUSH4State * env);
#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
#define cpu_list sh4_cpu_list

23
target/sparc/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU SPARC CPU
* QEMU SPARC CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,7 +21,6 @@
#define QEMU_SPARC_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#ifdef TARGET_SPARC64
#define TYPE_SPARC_CPU "sparc64-cpu"
@ -31,23 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
typedef struct sparc_def_t sparc_def_t;
/**
* SPARCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A SPARC CPU model.
*/
struct SPARCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
sparc_def_t *cpu_def;
};
#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
#endif

22
target/sparc/cpu.h
View file

@ -249,7 +249,7 @@ typedef struct trap_state {
#endif
#define TARGET_INSN_START_EXTRA_WORDS 1
struct sparc_def_t {
typedef struct sparc_def_t {
const char *name;
target_ulong iu_version;
uint32_t fpu_version;
@ -263,7 +263,7 @@ struct sparc_def_t {
uint32_t features;
uint32_t nwindows;
uint32_t maxtl;
};
} sparc_def_t;
#define FEATURE(X) CPU_FEATURE_BIT_##X,
enum {
@ -562,13 +562,25 @@ struct CPUArchState {
* A SPARC CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUSPARCState env;
};
/**
* SPARCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A SPARC CPU model.
*/
struct SPARCCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
sparc_def_t *cpu_def;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_sparc_cpu;
@ -656,8 +668,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
#endif
#endif
#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
#define cpu_list sparc_cpu_list

15
target/tricore/cpu-qom.h
View file

@ -1,4 +1,6 @@
/*
* QEMU TriCore CPU QOM header (target agnostic)
*
* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
*
* This library is free software; you can redistribute it and/or
@ -19,21 +21,12 @@
#define QEMU_TRICORE_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_TRICORE_CPU "tricore-cpu"
OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
struct TriCoreCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
#endif /* QEMU_TRICORE_CPU_QOM_H */

3
target/tricore/cpu.c
View file

@ -132,8 +132,7 @@ static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU) ||
object_class_is_abstract(oc)) {
if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU)) {
return NULL;
}
return oc;

10
target/tricore/cpu.h
View file

@ -63,13 +63,17 @@ typedef struct CPUArchState {
* A TriCore CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUTriCoreState env;
};
struct TriCoreCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
@ -270,8 +274,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
*flags = new_flags;
}
#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
/* helpers.c */

26
target/xtensa/cpu-qom.h
View file

@ -1,5 +1,5 @@
/*
* QEMU Xtensa CPU
* QEMU Xtensa CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
* All rights reserved.
@ -30,32 +30,12 @@
#define QEMU_XTENSA_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_XTENSA_CPU "xtensa-cpu"
OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
typedef struct XtensaConfig XtensaConfig;
/**
* XtensaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @config: The CPU core configuration.
*
* An Xtensa CPU model.
*/
struct XtensaCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
const XtensaConfig *config;
};
#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
#endif

3
target/xtensa/cpu.c
View file

@ -141,8 +141,7 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
object_class_is_abstract(oc)) {
if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU)) {
return NULL;
}
return oc;

24
target/xtensa/cpu.h
View file

@ -426,7 +426,7 @@ extern const XtensaOpcodeTranslators xtensa_core_opcodes;
extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
extern const XtensaOpcodeTranslators xtensa_fpu_opcodes;
struct XtensaConfig {
typedef struct XtensaConfig {
const char *name;
uint64_t options;
XtensaGdbRegmap gdb_regmap;
@ -489,7 +489,7 @@ struct XtensaConfig {
const xtensa_mpu_entry *mpu_bg;
bool use_first_nan;
};
} XtensaConfig;
typedef struct XtensaConfigList {
const XtensaConfig *config;
@ -556,14 +556,28 @@ struct CPUArchState {
* An Xtensa CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUXtensaState env;
Clock *clock;
};
/**
* XtensaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @config: The CPU core configuration.
*
* An Xtensa CPU model.
*/
struct XtensaCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
const XtensaConfig *config;
};
#ifndef CONFIG_USER_ONLY
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@ -588,8 +602,6 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
#define cpu_list xtensa_cpu_list
#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
#if TARGET_BIG_ENDIAN

4
target/xtensa/op_helper.c
View file

@ -37,7 +37,7 @@
void HELPER(update_ccount)(CPUXtensaState *env)
{
XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
XtensaCPU *cpu = env_archcpu(env);
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
env->ccount_time = now;
@ -58,7 +58,7 @@ void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
{
XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
XtensaCPU *cpu = env_archcpu(env);
uint64_t dcc;
qatomic_and(&env->sregs[INTSET],