mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 00:03:54 -06:00
Misc hardware patch queue
HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= =OVdQ -----END PGP SIGNATURE----- Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging Misc hardware patch queue HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t # wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S # vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q # jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi # zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh # ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan # DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM # L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu # DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z # HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY # Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp # 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= # =OVdQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits) dump: Add close fd on error return to avoid resource leak ui/sdl2: use correct key names in win title on mac MAINTAINERS: Add more guest-agent related files to the corresponding section MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section MAINTAINERS: update libvirt devel mailing list address MAINTAINERS: Add the CAN documentation file to the CAN section MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section hw/sd: Declare QOM types using DEFINE_TYPES() macro hw/i2c: pmbus: reset page register for out of range reads hw/i2c: pmbus: immediately clear faults on request tests/qtest: add tests for ADM1266 hw/sensor: add ADM1266 device model hw/i2c: pmbus: add VCAP register hw/i2c: pmbus: add fan support hw/i2c: pmbus: add vout mode bitfields hw/i2c: pmbus add support for block receive tests/qtest: ahci-test: add test exposing reset issue with pending callback hw/ide: reset: cancel async DMA operation before resetting state hw/cpu: Update the comments of nr_cores and nr_dies system/cpus: Fix CPUState.nr_cores' calculation ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
ed1d873caa
134 changed files with 1722 additions and 1085 deletions
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@ -45,9 +45,6 @@ void cpu_list_lock(void);
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void cpu_list_unlock(void);
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unsigned int cpu_list_generation_id_get(void);
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void tcg_flush_softmmu_tlb(CPUState *cs);
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void tcg_flush_jmp_cache(CPUState *cs);
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void tcg_iommu_init_notifier_list(CPUState *cpu);
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void tcg_iommu_free_notifier_list(CPUState *cpu);
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@ -23,4 +23,6 @@
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*/
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void tb_flush(CPUState *cs);
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void tcg_flush_jmp_cache(CPUState *cs);
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#endif /* _TB_FLUSH_H_ */
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@ -102,7 +102,7 @@ struct SysemuCPUOps;
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/**
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* CPUClass:
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* @class_by_name: Callback to map -cpu command line model name to an
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* instantiatable CPU type.
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* instantiatable CPU type.
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* @parse_features: Callback to parse command line arguments.
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* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
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* @has_work: Callback for checking if there is work to do.
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@ -408,7 +408,7 @@ struct qemu_work_item;
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* See TranslationBlock::TCG CF_CLUSTER_MASK.
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* @tcg_cflags: Pre-computed cflags for this cpu.
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* @nr_cores: Number of cores within this CPU package.
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* @nr_threads: Number of threads within this CPU.
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* @nr_threads: Number of threads within this CPU core.
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* @running: #true if CPU is currently running (lockless).
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* @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
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* valid under cpu_list_lock.
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@ -586,13 +586,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu)
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}
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typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
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extern CPUTailQ cpus;
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extern CPUTailQ cpus_queue;
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#define first_cpu QTAILQ_FIRST_RCU(&cpus)
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#define first_cpu QTAILQ_FIRST_RCU(&cpus_queue)
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#define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
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#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
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#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node)
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#define CPU_FOREACH_SAFE(cpu, next_cpu) \
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QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
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QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu)
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extern __thread CPUState *current_cpu;
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@ -772,9 +772,10 @@ void cpu_reset(CPUState *cpu);
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* @typename: The CPU base type.
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* @cpu_model: The model string without any parameters.
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*
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* Looks up a CPU #ObjectClass matching name @cpu_model.
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* Looks up a concrete CPU #ObjectClass matching name @cpu_model.
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*
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* Returns: A #CPUClass or %NULL if not matching class is found.
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* Returns: A concrete #CPUClass or %NULL if no matching class is found
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* or if the matching class is abstract.
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*/
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ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
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@ -1151,8 +1152,9 @@ G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
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/* $(top_srcdir)/cpu.c */
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void cpu_class_init_props(DeviceClass *dc);
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void cpu_exec_initfn(CPUState *cpu);
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void cpu_exec_realizefn(CPUState *cpu, Error **errp);
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bool cpu_exec_realizefn(CPUState *cpu, Error **errp);
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void cpu_exec_unrealizefn(CPUState *cpu);
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void cpu_exec_reset_hold(CPUState *cpu);
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/**
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* target_words_bigendian:
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@ -243,6 +243,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass,
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#define PB_HAS_VIN_RATING BIT_ULL(13)
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#define PB_HAS_VOUT_RATING BIT_ULL(14)
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#define PB_HAS_VOUT_MODE BIT_ULL(15)
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#define PB_HAS_VCAP BIT_ULL(16)
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#define PB_HAS_IOUT BIT_ULL(21)
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#define PB_HAS_IIN BIT_ULL(22)
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#define PB_HAS_IOUT_RATING BIT_ULL(23)
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@ -258,6 +259,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass,
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#define PB_HAS_TEMP2 BIT_ULL(41)
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#define PB_HAS_TEMP3 BIT_ULL(42)
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#define PB_HAS_TEMP_RATING BIT_ULL(43)
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#define PB_HAS_FAN BIT_ULL(44)
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#define PB_HAS_MFR_INFO BIT_ULL(50)
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#define PB_HAS_STATUS_MFR_SPECIFIC BIT_ULL(51)
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@ -444,6 +446,14 @@ typedef struct PMBusCoefficients {
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int32_t R; /* exponent */
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} PMBusCoefficients;
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/**
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* VOUT_Mode bit fields
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*/
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typedef struct PMBusVoutMode {
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uint8_t mode:3;
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int8_t exp:5;
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} PMBusVoutMode;
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/**
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* Convert sensor values to direct mode format
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*
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@ -501,6 +511,13 @@ void pmbus_send64(PMBusDevice *state, uint64_t data);
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*/
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void pmbus_send_string(PMBusDevice *state, const char *data);
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/**
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* @brief Receive data sent with Block Write.
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* @param dest - memory with enough capacity to receive the write
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* @param len - the capacity of dest
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*/
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uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len);
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/**
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* @brief Receive data over PMBus
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* These methods help track how much data is being received over PMBus
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@ -24,7 +24,8 @@
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#ifndef HW_I386_TOPOLOGY_H
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#define HW_I386_TOPOLOGY_H
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/* This file implements the APIC-ID-based CPU topology enumeration logic,
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/*
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* This file implements the APIC-ID-based CPU topology enumeration logic,
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* documented at the following document:
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* Intel® 64 Architecture Processor Topology Enumeration
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* http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
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@ -41,7 +42,8 @@
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#include "qemu/bitops.h"
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/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
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/*
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* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
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*/
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typedef uint32_t apic_id_t;
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@ -58,8 +60,7 @@ typedef struct X86CPUTopoInfo {
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unsigned threads_per_core;
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} X86CPUTopoInfo;
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/* Return the bit width needed for 'count' IDs
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*/
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/* Return the bit width needed for 'count' IDs */
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static unsigned apicid_bitwidth_for_count(unsigned count)
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{
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g_assert(count >= 1);
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@ -67,15 +68,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
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return count ? 32 - clz32(count) : 0;
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}
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/* Bit width of the SMT_ID (thread ID) field on the APIC ID
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*/
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/* Bit width of the SMT_ID (thread ID) field on the APIC ID */
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static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
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{
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return apicid_bitwidth_for_count(topo_info->threads_per_core);
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}
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/* Bit width of the Core_ID field
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*/
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/* Bit width of the Core_ID field */
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static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
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{
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return apicid_bitwidth_for_count(topo_info->cores_per_die);
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@ -87,8 +86,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
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return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
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}
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/* Bit offset of the Core_ID field
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*/
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/* Bit offset of the Core_ID field */
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static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
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{
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return apicid_smt_width(topo_info);
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@ -100,14 +98,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
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return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
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}
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/* Bit offset of the Pkg_ID (socket ID) field
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*/
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/* Bit offset of the Pkg_ID (socket ID) field */
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static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
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{
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return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
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}
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/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
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/*
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* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
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*
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* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
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*/
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@ -120,7 +118,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
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topo_ids->smt_id;
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}
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/* Calculate thread/core/package IDs for a specific topology,
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/*
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* Calculate thread/core/package IDs for a specific topology,
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* based on (contiguous) CPU index
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*/
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static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
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@ -137,7 +136,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
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topo_ids->smt_id = cpu_index % nr_threads;
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}
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/* Calculate thread/core/package IDs for a specific topology,
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/*
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* Calculate thread/core/package IDs for a specific topology,
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* based on APIC ID
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*/
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static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
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@ -155,7 +155,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
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topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
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}
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/* Make APIC ID for the CPU 'cpu_index'
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/*
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* Make APIC ID for the CPU 'cpu_index'
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*
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* 'cpu_index' is a sequential, contiguous ID for the CPU.
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*/
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@ -272,7 +272,7 @@ void pstrcpy_targphys(const char *name,
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ssize_t rom_add_file(const char *file, const char *fw_dir,
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hwaddr addr, int32_t bootindex,
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bool option_rom, MemoryRegion *mr, AddressSpace *as);
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bool has_option_rom, MemoryRegion *mr, AddressSpace *as);
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MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len,
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size_t max_len, hwaddr addr,
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const char *fw_file_name,
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@ -1,7 +1,7 @@
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#ifndef HW_PPC_H
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#define HW_PPC_H
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#include "target/ppc/cpu-qom.h"
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#include "target/ppc/cpu.h"
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void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
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PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
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@ -233,7 +233,7 @@ typedef enum {
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} CssIoAdapterType;
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void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
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int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
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int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode);
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uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
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void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
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uint8_t flags, Error **errp);
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@ -227,8 +227,7 @@ static inline int sccb_data_len(SCCB *sccb)
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void s390_sclp_init(void);
|
||||
void sclp_service_interrupt(uint32_t sccb);
|
||||
void raise_irq_cpu_hotplug(void);
|
||||
int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
|
||||
int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
|
||||
uint32_t code);
|
||||
int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code);
|
||||
int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ struct AccelOpsClass {
|
|||
void (*ops_init)(AccelOpsClass *ops);
|
||||
|
||||
bool (*cpus_are_resettable)(void);
|
||||
void (*cpu_reset_hold)(CPUState *cpu);
|
||||
|
||||
void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */
|
||||
void (*kick_vcpu_thread)(CPUState *cpu);
|
||||
|
|
|
|||
|
|
@ -521,7 +521,6 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source);
|
|||
* Returns: 0 on success, or a negative errno on failure.
|
||||
*/
|
||||
int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target);
|
||||
struct ppc_radix_page_info *kvm_get_radix_page_info(void);
|
||||
|
||||
/* Notify resamplefd for EOI of specific interrupts. */
|
||||
void kvm_resample_fd_notify(int gsi);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue