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aspeed: introduce a configurable number of CPU per machine

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The current models of the Aspeed SoCs only have one CPU but future
ones will support SMP. Introduce a new num_cpus field at the SoC class
level to define the number of available CPUs per SoC and also
introduce a 'num-cpus' property to activate the CPUs configured for
the machine.

The max_cpus limit of the machine should depend on the SoC definition
but, unfortunately, these values are not available when the machine
class is initialized. This is the reason why we add a check on
num_cpus in the AspeedSoC realize handler.

SMP support will be activated when models for such SoCs are implemented.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-6-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2019-07-01 17:26:16 +01:00 • committed by Peter Maydell
parent 75fb4577fc
commit ece09beec4
3 changed files with 36 additions and 9 deletions
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5
include/hw/arm/aspeed_soc.h
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@ -24,13 +24,15 @@
#define ASPEED_SPIS_NUM 2
#define ASPEED_WDTS_NUM 3
#define ASPEED_CPUS_NUM 2
typedef struct AspeedSoCState {
/*< private >*/
DeviceState parent;
/*< public >*/
ARMCPU cpu;
ARMCPU cpu[ASPEED_CPUS_NUM];
uint32_t num_cpus;
MemoryRegion sram;
AspeedVICState vic;
AspeedRtcState rtc;
@ -58,6 +60,7 @@ typedef struct AspeedSoCInfo {
int wdts_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
} AspeedSoCInfo;
typedef struct AspeedSoCClass {