motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 08:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

Browse source 
Move helper_cache() to tcg/sysemu/special_helper.c.

The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub helper to satisfy linking,
which abort if ever called.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-25-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-04-13 20:21:16 +02:00
parent d60146a938
commit ecdbcb0a94
5 changed files with 47 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/mips/helper.h
View file

@ -614,8 +614,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
DEF_HELPER_3(cache, void, env, tl, i32)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
#include "tcg/sysemu_helper.h.inc" #include "tcg/sysemu_helper.h.inc"
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */

35
target/mips/op_helper.c
View file

@ -788,38 +788,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
} }
} }
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
#ifndef CONFIG_USER_ONLY
static const char *const type_name[] = {
"Primary Instruction",
"Primary Data or Unified Primary",
"Tertiary",
"Secondary"
};
uint32_t cache_type = extract32(op, 0, 2);
uint32_t cache_operation = extract32(op, 2, 3);
target_ulong index = addr & 0x1fffffff;
switch (cache_operation) {
case 0b010: /* Index Store Tag */
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
break;
case 0b001: /* Index Load Tag */
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
break;
case 0b000: /* Index Invalidate */
case 0b100: /* Hit Invalidate */
case 0b110: /* Hit Writeback */
/* no-op */
break;
default:
qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
cache_operation, type_name[cache_type]);
break;
}
#endif
}

33
target/mips/tcg/sysemu/special_helper.c
View file

@ -138,3 +138,36 @@ void helper_deret(CPUMIPSState *env)
debug_post_eret(env); debug_post_eret(env);
} }
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
static const char *const type_name[] = {
"Primary Instruction",
"Primary Data or Unified Primary",
"Tertiary",
"Secondary"
};
uint32_t cache_type = extract32(op, 0, 2);
uint32_t cache_operation = extract32(op, 2, 3);
target_ulong index = addr & 0x1fffffff;
switch (cache_operation) {
case 0b010: /* Index Store Tag */
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
break;
case 0b001: /* Index Load Tag */
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
break;
case 0b000: /* Index Invalidate */
case 0b100: /* Hit Invalidate */
case 0b110: /* Hit Writeback */
/* no-op */
break;
default:
qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
cache_operation, type_name[cache_type]);
break;
}
}

1
target/mips/tcg/sysemu_helper.h.inc
View file

@ -173,3 +173,4 @@ DEF_HELPER_1(ei, tl, env)
DEF_HELPER_1(eret, void, env) DEF_HELPER_1(eret, void, env)
DEF_HELPER_1(eretnc, void, env) DEF_HELPER_1(eretnc, void, env)
DEF_HELPER_1(deret, void, env) DEF_HELPER_1(deret, void, env)
DEF_HELPER_3(cache, void, env, tl, i32)

13
target/mips/translate.c
View file

@ -39,6 +39,19 @@
#include "fpu_helper.h" #include "fpu_helper.h"
#include "translate.h" #include "translate.h"
/*
* Many sysemu-only helpers are not reachable for user-only.
* Define stub generators here, so that we need not either sprinkle
* ifdefs through the translator, nor provide the helper function.
*/
#define STUB_HELPER(NAME, ...) \
static inline void gen_helper_##NAME(__VA_ARGS__) \
{ g_assert_not_reached(); }
#ifdef CONFIG_USER_ONLY
STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg)
#endif
enum { enum {
/* indirect opcode tables */ /* indirect opcode tables */
OPC_SPECIAL = (0x00 << 26), OPC_SPECIAL = (0x00 << 26),