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target-arm queue:

Browse source 
* Implement FEAT_EBF16 emulation
  * accel/tcg: Remove dead code from rr_cpu_thread_fn()
  * hw: add compat machines for 9.2
  * virt: default to two-stage SMMU from virt-9.2
  * sbsa-ref: use two-stage SMMU
  * hw: Various minor memory leak fixes
  * target/arm: Correct names of VFP VFNMA and VFNMS insns
  * hw/arm/xilinx_zynq: Enable Security Extensions
  * hw/arm/boot: Report error msg if loading elf/dtb failed
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Merge tag 'pull-target-arm-20240905' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Implement FEAT_EBF16 emulation
 * accel/tcg: Remove dead code from rr_cpu_thread_fn()
 * hw: add compat machines for 9.2
 * virt: default to two-stage SMMU from virt-9.2
 * sbsa-ref: use two-stage SMMU
 * hw: Various minor memory leak fixes
 * target/arm: Correct names of VFP VFNMA and VFNMS insns
 * hw/arm/xilinx_zynq: Enable Security Extensions
 * hw/arm/boot: Report error msg if loading elf/dtb failed

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# gpg: Signature made Thu 05 Sep 2024 13:59:29 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240905' of https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits)
  platform-bus: fix refcount leak
  hw/arm/boot: Explain why load_elf_hdr() error is ignored
  hw/arm/boot: Report error msg if loading elf/dtb failed
  hw/arm/xilinx_zynq: Enable Security Extensions
  target/arm: Correct names of VFP VFNMA and VFNMS insns
  hw/arm/sbsa-ref: Don't leak string in sbsa_fdt_add_gic_node()
  hm/nvram/xlnx-versal-efuse-ctrl: Call register_finalize_block
  hw/misc/xlnx-versal-trng: Call register_finalize_block
  hw/nvram/xlnx-zynqmp-efuse: Call register_finalize_block
  hw/nvram/xlnx-bbram: Call register_finalize_block
  hw/misc/xlnx-versal-trng: Free s->prng in finalize, not unrealize
  hw/misc/xlnx-versal-cfu: destroy fifo in finalize
  hw/arm/sbsa-ref: Use two-stage SMMU
  hw/arm/virt: Default to two-stage SMMU from virt-9.2
  hw/arm/smmuv3: Update comment documenting "stage" property
  hw: add compat machines for 9.2
  accel/tcg: Remove dead code from rr_cpu_thread_fn()
  target/arm: Enable FEAT_EBF16 in the "max" CPU
  target/arm: Implement FPCR.EBF=1 semantics for bfdotadd()
  target/arm: Prepare bfdotadd() callers for FEAT_EBF support
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-09-06 13:59:37 +01:00
commit ec08d9a51e
42 changed files with 529 additions and 154 deletions
Download patch file Download diff file Expand all files Collapse all files

10
hw/arm/boot.c
View file

@ -799,14 +799,18 @@ static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
} elf_header;
int data_swab = 0;
bool big_endian;
ssize_t ret = -1;
ssize_t ret;
Error *err = NULL;
load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
if (err) {
/*
* If the file is not an ELF file we silently return.
* The caller will fall back to try other formats.
*/
error_free(err);
return ret;
return -1;
}
if (elf_is64) {
@ -839,6 +843,8 @@ static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
1, data_swab, as);
if (ret <= 0) {
/* The header loaded but the image didn't */
error_report("Couldn't load elf '%s': %s",
info->kernel_filename, load_elf_strerror(ret));
exit(1);
}

16
hw/arm/sbsa-ref.c
View file

@ -164,23 +164,20 @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
{
char *nodename;
const char *intc_nodename = "/intc";
const char *its_nodename = "/intc/its";
nodename = g_strdup_printf("/intc");
qemu_fdt_add_subnode(sms->fdt, nodename);
qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
qemu_fdt_add_subnode(sms->fdt, intc_nodename);
qemu_fdt_setprop_sized_cells(sms->fdt, intc_nodename, "reg",
2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
nodename = g_strdup_printf("/intc/its");
qemu_fdt_add_subnode(sms->fdt, nodename);
qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
qemu_fdt_add_subnode(sms->fdt, its_nodename);
qemu_fdt_setprop_sized_cells(sms->fdt, its_nodename, "reg",
2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
g_free(nodename);
}
/*
@ -621,6 +618,7 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
dev = qdev_new(TYPE_ARM_SMMUV3);
object_property_set_str(OBJECT(dev), "stage", "nested", &error_abort);
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

1
hw/arm/smmuv3.c
View file

@ -1981,6 +1981,7 @@ static Property smmuv3_properties[] = {
* Stages of translation advertised.
* "1": Stage 1
* "2": Stage 2
* "nested": Both stage 1 and stage 2
* Defaults to stage 1
*/
DEFINE_PROP_STRING("stage", SMMUv3State, stage),

19
hw/arm/virt.c
View file

@ -1408,6 +1408,7 @@ static void create_pcie_irq_map(const MachineState *ms,
static void create_smmu(const VirtMachineState *vms,
PCIBus *bus)
{
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
char *node;
const char compat[] = "arm,smmu-v3";
int irq = vms->irqmap[VIRT_SMMU];
@ -1424,6 +1425,9 @@ static void create_smmu(const VirtMachineState *vms,
dev = qdev_new(TYPE_ARM_SMMUV3);
if (!vmc->no_nested_smmu) {
object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal);
}
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -3301,10 +3305,21 @@ static void machvirt_machine_init(void)
}
type_init(machvirt_machine_init);
static void virt_machine_9_1_options(MachineClass *mc)
static void virt_machine_9_2_options(MachineClass *mc)
{
}
DEFINE_VIRT_MACHINE_AS_LATEST(9, 1)
DEFINE_VIRT_MACHINE_AS_LATEST(9, 2)
static void virt_machine_9_1_options(MachineClass *mc)
{
VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
virt_machine_9_2_options(mc);
compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
/* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
vmc->no_nested_smmu = true;
}
DEFINE_VIRT_MACHINE(9, 1)
static void virt_machine_9_0_options(MachineClass *mc)
{

8
hw/arm/xilinx_zynq.c
View file

@ -219,14 +219,6 @@ static void zynq_init(MachineState *machine)
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj = object_new(machine->cpu_type);
/*
* By default A9 CPUs have EL3 enabled. This board does not currently
* support EL3 so the CPU EL3 property is disabled before realization.
*/
if (object_property_find(cpuobj, "has_el3")) {
object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
}
object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR,
&error_fatal);
object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,