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hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out port (CFU_FDRO). Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230831165701.2016397-4-francisco.iglesias@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -20,10 +20,14 @@
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/misc/xlnx-cfi-if.h"
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#include "qemu/fifo32.h"
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#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
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#define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx,versal-cfu-fdro"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
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REG32(CFU_ISR, 0x0)
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FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
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FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
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@ -210,6 +214,14 @@ struct XlnxVersalCFUAPB {
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} cfg;
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};
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struct XlnxVersalCFUFDRO {
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SysBusDevice parent_obj;
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MemoryRegion iomem_fdro;
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Fifo32 fdro_data;
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};
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/**
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* This is a helper function for updating a CFI data write fifo, an array of 4
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* uint32_t and 128 bits of data that are allowed to be written through 4
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