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target/arm: Fault on invalid TCR_ELx.TxSZ

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Without FEAT_LVA, the behaviour of programming an invalid value
is IMPLEMENTATION DEFINED.  With FEAT_LVA, programming an invalid
minimum value requires a Translation fault.

It is most self-consistent to choose to generate the fault always.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-03-01 11:59:43 -10:00 • committed by Peter Maydell
parent 691f1ffdfc
commit ebf93ce7c0
2 changed files with 29 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

32
target/arm/helper.c
View file

@ -11190,8 +11190,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
ARMMMUIdx mmu_idx, bool data) ARMMMUIdx mmu_idx, bool data)
{ {
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
bool epd, hpd, using16k, using64k; bool epd, hpd, using16k, using64k, tsz_oob;
int select, tsz, tbi, max_tsz; int select, tsz, tbi, max_tsz, min_tsz;
if (!regime_has_2_ranges(mmu_idx)) { if (!regime_has_2_ranges(mmu_idx)) {
select = 0; select = 0;
@ -11232,9 +11232,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
} else { } else {
max_tsz = 39; max_tsz = 39;
} }
min_tsz = 16; /* TODO: ARMv8.2-LVA */
tsz = MIN(tsz, max_tsz); if (tsz > max_tsz) {
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ tsz = max_tsz;
tsz_oob = true;
} else if (tsz < min_tsz) {
tsz = min_tsz;
tsz_oob = true;
} else {
tsz_oob = false;
}
/* Present TBI as a composite with TBID. */ /* Present TBI as a composite with TBID. */
tbi = aa64_va_parameter_tbi(tcr, mmu_idx); tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
@ -11251,6 +11259,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
.hpd = hpd, .hpd = hpd,
.using16k = using16k, .using16k = using16k,
.using64k = using64k, .using64k = using64k,
.tsz_oob = tsz_oob,
}; };
} }
@ -11374,6 +11383,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
param = aa64_va_parameters(env, address, mmu_idx, param = aa64_va_parameters(env, address, mmu_idx,
access_type != MMU_INST_FETCH); access_type != MMU_INST_FETCH);
level = 0; level = 0;
/*
* If TxSZ is programmed to a value larger than the maximum,
* or smaller than the effective minimum, it is IMPLEMENTATION
* DEFINED whether we behave as if the field were programmed
* within bounds, or if a level 0 Translation fault is generated.
*
* With FEAT_LVA, fault on less than minimum becomes required,
* so our choice is to always raise the fault.
*/
if (param.tsz_oob) {
fault_type = ARMFault_Translation;
goto do_fault;
}
addrsize = 64 - 8 * param.tbi; addrsize = 64 - 8 * param.tbi;
inputsize = 64 - param.tsz; inputsize = 64 - param.tsz;
} else { } else {

1
target/arm/internals.h
View file

@ -1055,6 +1055,7 @@ typedef struct ARMVAParameters {
bool hpd : 1; bool hpd : 1;
bool using16k : 1; bool using16k : 1;
bool using64k : 1; bool using64k : 1;
bool tsz_oob : 1; /* tsz has been clamped to legal range */
} ARMVAParameters; } ARMVAParameters;
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,