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tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}

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Interpret the variable argument placement in the caller.  There are
several places where we already convert back from bool to type.
Clean things up by using type throughout.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-06 12:52:26 -07:00
parent 9a2027b7a2
commit eb664d0c52
1 changed files with 95 additions and 91 deletions
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186
tcg/mips/tcg-target.c.inc
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@ -1479,7 +1479,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
#endif /* SOFTMMU */ #endif /* SOFTMMU */
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc, bool is_64) TCGReg base, MemOp opc, TCGType type)
{ {
switch (opc & (MO_SSIZE | MO_BSWAP)) { switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB: case MO_UB:
@ -1503,7 +1503,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_LH, lo, base, 0); tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
break; break;
case MO_UL | MO_BSWAP: case MO_UL | MO_BSWAP:
if (TCG_TARGET_REG_BITS == 64 && is_64) { if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
if (use_mips32r2_instructions) { if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
@ -1528,7 +1528,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
} }
break; break;
case MO_UL: case MO_UL:
if (TCG_TARGET_REG_BITS == 64 && is_64) { if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
break; break;
} }
@ -1583,7 +1583,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
} }
static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc, bool is_64) TCGReg base, MemOp opc, TCGType type)
{ {
const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL; const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
@ -1623,7 +1623,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_UL: case MO_UL:
tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw1, lo, base, 0);
tcg_out_opc_imm(s, lw2, lo, base, 3); tcg_out_opc_imm(s, lw2, lo, base, 3);
if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) { if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {
tcg_out_ext32u(s, lo, lo); tcg_out_ext32u(s, lo, lo);
} }
break; break;
@ -1634,18 +1634,18 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw1, lo, base, 0);
tcg_out_opc_imm(s, lw2, lo, base, 3); tcg_out_opc_imm(s, lw2, lo, base, 3);
tcg_out_bswap32(s, lo, lo, tcg_out_bswap32(s, lo, lo,
TCG_TARGET_REG_BITS == 64 && is_64 TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64
? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0);
} else { } else {
const tcg_insn_unit *subr = const tcg_insn_unit *subr =
(TCG_TARGET_REG_BITS == 64 && is_64 && !sgn (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn
? bswap32u_addr : bswap32_addr); ? bswap32u_addr : bswap32_addr);
tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0);
tcg_out_bswap_subr(s, subr); tcg_out_bswap_subr(s, subr);
/* delay slot */ /* delay slot */
tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3);
tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3); tcg_out_mov(s, type, lo, TCG_TMP3);
} }
break; break;
@ -1702,68 +1702,59 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
} }
} }
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
MemOpIdx oi, TCGType data_type)
{ {
TCGReg addr_regl, addr_regh __attribute__((unused)); MemOp opc = get_memop(oi);
TCGReg data_regl, data_regh; unsigned a_bits = get_alignment_bits(opc);
MemOpIdx oi; unsigned s_bits = opc & MO_SIZE;
MemOp opc; TCGReg base;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
#else
#endif
unsigned a_bits, s_bits;
TCGReg base = TCG_REG_A0;
data_regl = *args++;
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
addr_regl = *args++;
addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
oi = *args++;
opc = get_memop(oi);
a_bits = get_alignment_bits(opc);
s_bits = opc & MO_SIZE;
/* /*
* R6 removes the left/right instructions but requires the * R6 removes the left/right instructions but requires the
* system to support misaligned memory accesses. * system to support misaligned memory accesses.
*/ */
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); tcg_insn_unit *label_ptr[2];
base = TCG_REG_A0;
tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1);
if (use_mips32r6_instructions || a_bits >= s_bits) { if (use_mips32r6_instructions || a_bits >= s_bits) {
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
} else { } else {
tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type);
} }
add_qemu_ldst_label(s, 1, oi, add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), addrlo, addrhi, s->code_ptr, label_ptr);
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else #else
base = addrlo;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, base, addr_regl); tcg_out_ext32u(s, TCG_REG_A0, base);
addr_regl = base; base = TCG_REG_A0;
} }
if (guest_base == 0 && data_regl != addr_regl) { if (guest_base) {
base = addr_regl; if (guest_base == (int16_t)guest_base) {
} else if (guest_base == (int16_t)guest_base) { tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); } else {
} else { tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); TCG_GUEST_BASE_REG);
}
base = TCG_REG_A0;
} }
if (use_mips32r6_instructions) { if (use_mips32r6_instructions) {
if (a_bits) { if (a_bits) {
tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
} }
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
} else { } else {
if (a_bits && a_bits != s_bits) { if (a_bits && a_bits != s_bits) {
tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
} }
if (a_bits >= s_bits) { if (a_bits >= s_bits) {
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
} else { } else {
tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type);
} }
} }
#endif #endif
@ -1902,67 +1893,60 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
g_assert_not_reached(); g_assert_not_reached();
} }
} }
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
#endif
unsigned a_bits, s_bits;
TCGReg base = TCG_REG_A0;
data_regl = *args++; static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); TCGReg addrlo, TCGReg addrhi,
addr_regl = *args++; MemOpIdx oi, TCGType data_type)
addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); {
oi = *args++; MemOp opc = get_memop(oi);
opc = get_memop(oi); unsigned a_bits = get_alignment_bits(opc);
a_bits = get_alignment_bits(opc); unsigned s_bits = opc & MO_SIZE;
s_bits = opc & MO_SIZE; TCGReg base;
/* /*
* R6 removes the left/right instructions but requires the * R6 removes the left/right instructions but requires the
* system to support misaligned memory accesses. * system to support misaligned memory accesses.
*/ */
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); tcg_insn_unit *label_ptr[2];
base = TCG_REG_A0;
tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0);
if (use_mips32r6_instructions || a_bits >= s_bits) { if (use_mips32r6_instructions || a_bits >= s_bits) {
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
} else { } else {
tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc);
} }
add_qemu_ldst_label(s, 0, oi, add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), addrlo, addrhi, s->code_ptr, label_ptr);
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else #else
base = addrlo;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, base, addr_regl); tcg_out_ext32u(s, TCG_REG_A0, base);
addr_regl = base; base = TCG_REG_A0;
} }
if (guest_base == 0) { if (guest_base) {
base = addr_regl; if (guest_base == (int16_t)guest_base) {
} else if (guest_base == (int16_t)guest_base) { tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); } else {
} else { tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); TCG_GUEST_BASE_REG);
}
base = TCG_REG_A0;
} }
if (use_mips32r6_instructions) { if (use_mips32r6_instructions) {
if (a_bits) { if (a_bits) {
tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
} }
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
} else { } else {
if (a_bits && a_bits != s_bits) { if (a_bits && a_bits != s_bits) {
tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
} }
if (a_bits >= s_bits) { if (a_bits >= s_bits) {
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
} else { } else {
tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc);
} }
} }
#endif #endif
@ -2425,16 +2409,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break; break;
case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, args, false); if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
} else {
tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
}
break; break;
case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_ld_i64:
tcg_out_qemu_ld(s, args, true); if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
} else if (TARGET_LONG_BITS == 32) {
tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
} else {
tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
}
break; break;
case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i32:
tcg_out_qemu_st(s, args, false); if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
} else {
tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
}
break; break;
case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i64:
tcg_out_qemu_st(s, args, true); if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
} else if (TARGET_LONG_BITS == 32) {
tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
} else {
tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
}
break; break;
case INDEX_op_add2_i32: case INDEX_op_add2_i32: