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pc,pci,virtio fixes and cleanups

Browse source 
This includes pc and pci cleanups and enhancements,
 and a virtio-net bugfix related to softmac programming.
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge remote-tracking branch 'mst/tags/for_anthony' into staging

pc,pci,virtio fixes and cleanups

This includes pc and pci cleanups and enhancements,
and a virtio-net bugfix related to softmac programming.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Sun 29 Sep 2013 01:51:16 AM CDT using RSA key ID D28D5469
# gpg: Can't check signature: public key not found

# By Michael S. Tsirkin (8) and others
# Via Michael S. Tsirkin
* mst/tags/for_anthony:
  smbios: Factor out smbios_maybe_add_str()
  smbios: Make multiple -smbios type= accumulate sanely
  smbios: Improve diagnostics for conflicting entries
  smbios: Convert to QemuOpts
  smbios: Normalize smbios_entry_add()'s error handling to exit(1)
  virtio-net: fix up HMP NIC info string on reset
  pci: remove explicit check to 64K ioport size
  piix4: disable io on reset
  piix: use 64 bit window programmed by guest
  q35: use 64 bit window programmed by guest
  pci: add helper to retrieve the 64-bit range
  range: add min/max operations on ranges
  range: add Range to typedefs
  q35: make pci window address/size match guest cfg

Message-id: 1380437951-21788-1-git-send-email-mst@redhat.com
This commit is contained in:
Anthony Liguori 2013-09-30 17:15:01 -05:00
commit eb322b8155
14 changed files with 358 additions and 119 deletions
Download patch file Download diff file Expand all files Collapse all files

24
hw/pci-host/q35.c
View file

@ -89,18 +89,24 @@ static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
void *opaque, const char *name,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
Range w64;
visit_type_uint64(v, &s->mch.pci_info.w64.begin, name, errp);
pci_bus_get_w64_range(h->bus, &w64);
visit_type_uint64(v, &w64.begin, name, errp);
}
static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
void *opaque, const char *name,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
Range w64;
visit_type_uint64(v, &s->mch.pci_info.w64.end, name, errp);
pci_bus_get_w64_range(h->bus, &w64);
visit_type_uint64(v, &w64.end, name, errp);
}
static Property mch_props[] = {
@ -214,6 +220,16 @@ static void mch_update_pciexbar(MCHPCIState *mch)
}
addr = pciexbar & addr_mask;
pcie_host_mmcfg_update(pehb, enable, addr, length);
/* Leave enough space for the MCFG BAR */
/*
* TODO: this matches current bios behaviour, but it's not a power of two,
* which means an MTRR can't cover it exactly.
*/
if (enable) {
mch->pci_info.w32.begin = addr + length;
} else {
mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
}
}
/* PAM */