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target/hppa: Add pa2.0 cpu local tlb flushes

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The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".

PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Helge Deller 2023-10-26 21:41:41 -07:00 • committed by Richard Henderson
parent b5caa17cda
commit eb25d10f4d
5 changed files with 84 additions and 12 deletions
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20
target/hppa/insns.decode
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@ -161,9 +161,23 @@ ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
# pa2.0 tlb insert idtlbt and iitlbt instructions
ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt
pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
sp=%assemble_sr3x data=0
# pdtlb, pitlb
pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \
&ldst disp=0 scale=0 size=0 t=0
pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \
&ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x
# ... pa20 local
pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \
&ldst disp=0 scale=0 size=0 t=0
pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \
&ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x
# pdtlbe, pitlbe
pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \
&ldst disp=0 scale=0 size=0 t=0
pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \
&ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x
lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
&ldst disp=0 scale=0 size=0